msm_readl          84 drivers/gpu/drm/msm/adreno/a6xx_gmu.h 	return msm_readl(gmu->mmio + (offset << 2));
msm_readl         105 drivers/gpu/drm/msm/adreno/a6xx_gmu.h 	val = (u64) msm_readl(gmu->mmio + (lo << 2));
msm_readl         106 drivers/gpu/drm/msm/adreno/a6xx_gmu.h 	val |= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32);
msm_readl         180 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	msm_readl((ptr) + ((offset) << 2))
msm_readl          58 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h 	return msm_readl(mdp4_kms->mmio + reg);
msm_readl         179 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h 	return msm_readl(mdp5_kms->mmio + reg);
msm_readl          38 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	return msm_readl(mdp5_mdss->mmio + reg);
msm_readl          49 drivers/gpu/drm/msm/dsi/dsi_host.c 	ver = msm_readl(base + REG_DSI_VERSION);
msm_readl          67 drivers/gpu/drm/msm/dsi/dsi_host.c 		ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
msm_readl          72 drivers/gpu/drm/msm/dsi/dsi_host.c 			*minor = msm_readl(base + REG_DSI_6G_HW_VERSION);
msm_readl         188 drivers/gpu/drm/msm/dsi/dsi_host.c 	return msm_readl(msm_host->ctrl_base + reg);
msm_readl          13 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h #define dsi_phy_read(offset) msm_readl((offset))
msm_readl          49 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h 	return msm_readl(reg);
msm_readl          18 drivers/gpu/drm/msm/edp/edp.h #define edp_read(offset) msm_readl((offset))
msm_readl         124 drivers/gpu/drm/msm/hdmi/hdmi.h 	return msm_readl(hdmi->mmio + reg);
msm_readl         129 drivers/gpu/drm/msm/hdmi/hdmi.h 	return msm_readl(hdmi->qfprom_mmio + reg);
msm_readl         175 drivers/gpu/drm/msm/hdmi/hdmi.h 	return msm_readl(phy->mmio + reg);
msm_readl          94 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 	return msm_readl(pll->mmio_qserdes_com + offset);
msm_readl         244 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c 	return msm_readl(pll->mmio + reg);
msm_readl         411 drivers/gpu/drm/msm/msm_drv.h u32 msm_readl(const void __iomem *addr);
msm_readl         221 drivers/gpu/drm/msm/msm_gpu.h 	return msm_readl(gpu->mmio + (reg << 2));
msm_readl         250 drivers/gpu/drm/msm/msm_gpu.h 	val = (u64) msm_readl(gpu->mmio + (lo << 2));
msm_readl         251 drivers/gpu/drm/msm/msm_gpu.h 	val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32);