msic_dcr_write    329 arch/powerpc/platforms/cell/axon_msi.c 	msic_dcr_write(msic, MSIC_CTRL_REG, tmp);
msic_dcr_write    394 arch/powerpc/platforms/cell/axon_msi.c 	msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32);
msic_dcr_write    395 arch/powerpc/platforms/cell/axon_msi.c 	msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG,
msic_dcr_write    397 arch/powerpc/platforms/cell/axon_msi.c 	msic_dcr_write(msic, MSIC_CTRL_REG,