mpll 60 arch/arm/mach-s3c24xx/cpufreq-utils.c if (!IS_ERR(cfg->mpll)) mpll 61 arch/arm/mach-s3c24xx/cpufreq-utils.c clk_set_rate(cfg->mpll, cfg->pll.frequency); mpll 118 arch/arm/plat-samsung/include/plat/cpu-freq-core.h struct clk *mpll; mpll 91 drivers/clk/imx/clk-imx25.c clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "mpll", "osc", ccm(CCM_MPCTL)); mpll 69 drivers/clk/imx/clk-imx31.c clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL); mpll 117 drivers/clk/imx/clk-imx35.c clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); mpll 120 drivers/clk/imx/clk-imx35.c clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4); mpll 79 drivers/clk/meson/clk-mpll.c struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); mpll 83 drivers/clk/meson/clk-mpll.c sdm = meson_parm_read(clk->map, &mpll->sdm); mpll 84 drivers/clk/meson/clk-mpll.c n2 = meson_parm_read(clk->map, &mpll->n2); mpll 95 drivers/clk/meson/clk-mpll.c struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); mpll 98 drivers/clk/meson/clk-mpll.c params_from_rate(rate, *parent_rate, &sdm, &n2, mpll->flags); mpll 107 drivers/clk/meson/clk-mpll.c struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); mpll 111 drivers/clk/meson/clk-mpll.c params_from_rate(rate, parent_rate, &sdm, &n2, mpll->flags); mpll 113 drivers/clk/meson/clk-mpll.c if (mpll->lock) mpll 114 drivers/clk/meson/clk-mpll.c spin_lock_irqsave(mpll->lock, flags); mpll 116 drivers/clk/meson/clk-mpll.c __acquire(mpll->lock); mpll 119 drivers/clk/meson/clk-mpll.c meson_parm_write(clk->map, &mpll->sdm, sdm); mpll 122 drivers/clk/meson/clk-mpll.c meson_parm_write(clk->map, &mpll->n2, n2); mpll 124 drivers/clk/meson/clk-mpll.c if (mpll->lock) mpll 125 drivers/clk/meson/clk-mpll.c spin_unlock_irqrestore(mpll->lock, flags); mpll 127 drivers/clk/meson/clk-mpll.c __release(mpll->lock); mpll 135 drivers/clk/meson/clk-mpll.c struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); mpll 137 drivers/clk/meson/clk-mpll.c if (mpll->init_count) mpll 138 drivers/clk/meson/clk-mpll.c regmap_multi_reg_write(clk->map, mpll->init_regs, mpll 139 drivers/clk/meson/clk-mpll.c mpll->init_count); mpll 142 drivers/clk/meson/clk-mpll.c meson_parm_write(clk->map, &mpll->sdm_en, 1); mpll 145 drivers/clk/meson/clk-mpll.c if (MESON_PARM_APPLICABLE(&mpll->ssen)) { mpll 147 drivers/clk/meson/clk-mpll.c mpll->flags & CLK_MESON_MPLL_SPREAD_SPECTRUM ? 1 : 0; mpll 148 drivers/clk/meson/clk-mpll.c meson_parm_write(clk->map, &mpll->ssen, ss); mpll 152 drivers/clk/meson/clk-mpll.c if (MESON_PARM_APPLICABLE(&mpll->misc)) mpll 153 drivers/clk/meson/clk-mpll.c meson_parm_write(clk->map, &mpll->misc, 1); mpll 1149 drivers/clk/samsung/clk-exynos4.c [mpll] = PLL(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", mpll 1160 drivers/clk/samsung/clk-exynos4.c [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", mpll 735 drivers/clk/samsung/clk-exynos5250.c [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, mpll 246 drivers/clk/samsung/clk-exynos5410.c [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, mpll 1460 drivers/clk/samsung/clk-exynos5420.c [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, mpll 154 drivers/clk/samsung/clk-s3c2410.c [mpll] = PLL(pll_s3c2410_mpll, MPLL, "mpll", "xti", mpll 220 drivers/clk/samsung/clk-s3c2410.c [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti", mpll 341 drivers/clk/samsung/clk-s3c2410.c s3c2410_plls[mpll].rate_table = pll_s3c2410_12mhz_tbl; mpll 355 drivers/clk/samsung/clk-s3c2410.c s3c244x_common_plls[mpll].rate_table = mpll 718 drivers/clk/samsung/clk-s5pv210.c [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll", mpll 730 drivers/clk/samsung/clk-s5pv210.c [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll", mpll 142 drivers/cpufreq/s3c24xx-cpufreq.c cfg->mpll = _clk_mpll; mpll 317 drivers/gpu/drm/amd/amdgpu/amdgpu.h struct amdgpu_pll mpll; mpll 571 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c struct amdgpu_pll *mpll = &adev->clock.mpll; mpll 643 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c mpll->reference_freq = mpll 645 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c mpll->reference_div = 0; mpll 647 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c mpll->pll_out_min = mpll 649 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c mpll->pll_out_max = mpll 653 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c if (mpll->pll_out_min == 0) mpll 654 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c mpll->pll_out_min = 64800; mpll 656 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c mpll->pll_in_min = mpll 658 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c mpll->pll_in_max = mpll 666 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c mpll->min_post_div = 1; mpll 667 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c mpll->max_post_div = 1; mpll 668 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c mpll->min_ref_div = 2; mpll 669 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c mpll->max_ref_div = 0xff; mpll 670 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c mpll->min_feedback_div = 4; mpll 671 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c mpll->max_feedback_div = 0xff; mpll 672 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c mpll->best_vco = 0; mpll 347 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c struct amdgpu_pll *mpll = &adev->clock.mpll; mpll 407 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz); mpll 409 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c mpll->reference_div = 0; mpll 410 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c mpll->min_post_div = 1; mpll 411 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c mpll->max_post_div = 1; mpll 412 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c mpll->min_ref_div = 2; mpll 413 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c mpll->max_ref_div = 0xff; mpll 414 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c mpll->min_feedback_div = 4; mpll 415 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c mpll->max_feedback_div = 0xff; mpll 416 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c mpll->best_vco = 0; mpll 5380 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 reference_clock = adev->clock.mpll.reference_freq; mpll 288 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c bool mpll = Preg == 0x4020; mpll 291 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) | mpll 306 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c if (mpll) { mpll 322 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c Pval |= mpll ? 1 << 12 : 1 << 8; mpll 326 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c if (mpll) { mpll 340 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c if (mpll) { mpll 349 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c if (mpll) { mpll 226 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct nvbios_pll mpll; mpll 328 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ret = nvbios_pll_parse(bios, 0x004008, &mpll); mpll 329 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c mpll.vco2.max_freq = 0; mpll 331 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ret = nv04_pll_calc(subdev, &mpll, freq, mpll 349 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c r004008 |= (mpll.bias_p << 19) | (P << 22) | (P << 16); mpll 2831 drivers/gpu/drm/radeon/ci_dpm.c u32 reference_clock = rdev->clock.mpll.reference_freq; mpll 444 drivers/gpu/drm/radeon/cypress_dpm.c u32 ref_clk = rdev->clock.mpll.reference_freq; mpll 560 drivers/gpu/drm/radeon/cypress_dpm.c u32 reference_clock = rdev->clock.mpll.reference_freq; mpll 2242 drivers/gpu/drm/radeon/ni_dpm.c u32 reference_clock = rdev->clock.mpll.reference_freq; mpll 268 drivers/gpu/drm/radeon/radeon.h struct radeon_pll mpll; mpll 1149 drivers/gpu/drm/radeon/radeon_atombios.c struct radeon_pll *mpll = &rdev->clock.mpll; mpll 1228 drivers/gpu/drm/radeon/radeon_atombios.c mpll->reference_freq = mpll 1231 drivers/gpu/drm/radeon/radeon_atombios.c mpll->reference_freq = mpll 1233 drivers/gpu/drm/radeon/radeon_atombios.c mpll->reference_div = 0; mpll 1235 drivers/gpu/drm/radeon/radeon_atombios.c mpll->pll_out_min = mpll 1237 drivers/gpu/drm/radeon/radeon_atombios.c mpll->pll_out_max = mpll 1241 drivers/gpu/drm/radeon/radeon_atombios.c if (mpll->pll_out_min == 0) { mpll 1243 drivers/gpu/drm/radeon/radeon_atombios.c mpll->pll_out_min = 64800; mpll 1245 drivers/gpu/drm/radeon/radeon_atombios.c mpll->pll_out_min = 20000; mpll 1248 drivers/gpu/drm/radeon/radeon_atombios.c mpll->pll_in_min = mpll 1250 drivers/gpu/drm/radeon/radeon_atombios.c mpll->pll_in_max = mpll 71 drivers/gpu/drm/radeon/radeon_clocks.c struct radeon_pll *mpll = &rdev->clock.mpll; mpll 77 drivers/gpu/drm/radeon/radeon_clocks.c fb_div *= mpll->reference_freq; mpll 111 drivers/gpu/drm/radeon/radeon_clocks.c struct radeon_pll *mpll = &rdev->clock.mpll; mpll 149 drivers/gpu/drm/radeon/radeon_clocks.c spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; mpll 150 drivers/gpu/drm/radeon/radeon_clocks.c spll->reference_div = mpll->reference_div = mpll 186 drivers/gpu/drm/radeon/radeon_clocks.c struct radeon_pll *mpll = &rdev->clock.mpll; mpll 218 drivers/gpu/drm/radeon/radeon_clocks.c if (mpll->reference_div < 2) mpll 219 drivers/gpu/drm/radeon/radeon_clocks.c mpll->reference_div = spll->reference_div; mpll 233 drivers/gpu/drm/radeon/radeon_clocks.c mpll->reference_freq = 1432; mpll 238 drivers/gpu/drm/radeon/radeon_clocks.c mpll->reference_freq = 2700; mpll 269 drivers/gpu/drm/radeon/radeon_clocks.c mpll->reference_div = spll->reference_div; mpll 331 drivers/gpu/drm/radeon/radeon_clocks.c mpll->min_post_div = 1; mpll 332 drivers/gpu/drm/radeon/radeon_clocks.c mpll->max_post_div = 1; mpll 333 drivers/gpu/drm/radeon/radeon_clocks.c mpll->min_ref_div = 2; mpll 334 drivers/gpu/drm/radeon/radeon_clocks.c mpll->max_ref_div = 0xff; mpll 335 drivers/gpu/drm/radeon/radeon_clocks.c mpll->min_feedback_div = 4; mpll 336 drivers/gpu/drm/radeon/radeon_clocks.c mpll->max_feedback_div = 0xff; mpll 337 drivers/gpu/drm/radeon/radeon_clocks.c mpll->best_vco = 0; mpll 739 drivers/gpu/drm/radeon/radeon_combios.c struct radeon_pll *mpll = &rdev->clock.mpll; mpll 780 drivers/gpu/drm/radeon/radeon_combios.c mpll->reference_freq = RBIOS16(pll_info + 0x26); mpll 781 drivers/gpu/drm/radeon/radeon_combios.c mpll->reference_div = RBIOS16(pll_info + 0x28); mpll 782 drivers/gpu/drm/radeon/radeon_combios.c mpll->pll_out_min = RBIOS32(pll_info + 0x2a); mpll 783 drivers/gpu/drm/radeon/radeon_combios.c mpll->pll_out_max = RBIOS32(pll_info + 0x2e); mpll 786 drivers/gpu/drm/radeon/radeon_combios.c mpll->pll_in_min = RBIOS32(pll_info + 0x5a); mpll 787 drivers/gpu/drm/radeon/radeon_combios.c mpll->pll_in_max = RBIOS32(pll_info + 0x5e); mpll 790 drivers/gpu/drm/radeon/radeon_combios.c mpll->pll_in_min = 40; mpll 791 drivers/gpu/drm/radeon/radeon_combios.c mpll->pll_in_max = 500; mpll 655 drivers/gpu/drm/radeon/rv6xx_dpm.c u32 ref_clk = rdev->clock.mpll.reference_freq; mpll 171 drivers/gpu/drm/radeon/rv730_dpm.c u32 reference_clock = rdev->clock.mpll.reference_freq; mpll 251 drivers/gpu/drm/radeon/rv740_dpm.c u32 reference_clock = rdev->clock.mpll.reference_freq; mpll 403 drivers/gpu/drm/radeon/rv770_dpm.c u32 reference_clock = rdev->clock.mpll.reference_freq; mpll 4918 drivers/gpu/drm/radeon/si_dpm.c u32 reference_clock = rdev->clock.mpll.reference_freq;