mphy_set_bit 96 drivers/phy/mediatek/phy-mtk-ufs.c mphy_set_bit(phy, MP_GLB_DIG_8C, PLL_PWR_ON); mphy_set_bit 104 drivers/phy/mediatek/phy-mtk-ufs.c mphy_set_bit(phy, MP_LN_RX_44, CDR_PWR_ON); mphy_set_bit 112 drivers/phy/mediatek/phy-mtk-ufs.c mphy_set_bit(phy, MP_LN_DIG_RX_AC, RX_SQ_EN); mphy_set_bit 125 drivers/phy/mediatek/phy-mtk-ufs.c mphy_set_bit(phy, MP_LN_DIG_RX_9C, FSM_DIFZ_FRC); mphy_set_bit 128 drivers/phy/mediatek/phy-mtk-ufs.c mphy_set_bit(phy, MP_LN_DIG_RX_AC, FRC_RX_SQ_EN); mphy_set_bit 132 drivers/phy/mediatek/phy-mtk-ufs.c mphy_set_bit(phy, MP_LN_RX_44, FRC_CDR_ISO_EN); mphy_set_bit 133 drivers/phy/mediatek/phy-mtk-ufs.c mphy_set_bit(phy, MP_LN_RX_44, CDR_ISO_EN); mphy_set_bit 136 drivers/phy/mediatek/phy-mtk-ufs.c mphy_set_bit(phy, MP_LN_RX_44, FRC_CDR_PWR_ON); mphy_set_bit 140 drivers/phy/mediatek/phy-mtk-ufs.c mphy_set_bit(phy, MP_GLB_DIG_8C, FRC_PLL_ISO_EN); mphy_set_bit 141 drivers/phy/mediatek/phy-mtk-ufs.c mphy_set_bit(phy, MP_GLB_DIG_8C, PLL_ISO_EN); mphy_set_bit 144 drivers/phy/mediatek/phy-mtk-ufs.c mphy_set_bit(phy, MP_GLB_DIG_8C, FRC_FRC_PWR_ON);