mpcc 983 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct mpcc *mpcc_to_remove = NULL; mpcc 2189 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct mpcc *new_mpcc; mpcc 68 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); mpcc 78 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpcc->blnd_cfg = *blnd_cfg; mpcc 106 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c struct mpcc *mpc1_get_mpcc(struct mpc *mpc, int mpcc_id) mpcc 114 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c struct mpcc *mpc1_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id) mpcc 116 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c struct mpcc *tmp_mpcc = tree->opp_list; mpcc 176 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c struct mpcc *mpc1_insert_plane( mpcc 181 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c struct mpcc *insert_above_mpcc, mpcc 186 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c struct mpcc *new_mpcc = NULL; mpcc 194 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c struct mpcc *temp_mpcc = tree->opp_list; mpcc 226 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c struct mpcc *temp_mpcc = tree->opp_list; mpcc 267 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c struct mpcc *mpcc_to_remove) mpcc 287 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c struct mpcc *temp_mpcc = tree->opp_list; mpcc 327 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst) mpcc 329 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpcc->mpcc_id = mpcc_inst; mpcc 330 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpcc->dpp_id = 0xf; mpcc 331 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpcc->mpcc_bot = NULL; mpcc 332 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpcc->blnd_cfg.overlap_only = false; mpcc 333 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpcc->blnd_cfg.global_alpha = 0xff; mpcc 334 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpcc->blnd_cfg.global_gain = 0xff; mpcc 335 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpcc->sm_cfg.enable = false; mpcc 394 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c struct mpcc *mpcc; mpcc 410 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpcc = mpc1_get_mpcc(mpc, mpcc_id); mpcc 411 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpcc->dpp_id = top_sel; mpcc 415 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c tree->opp_list = mpcc; mpcc 421 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c struct mpcc *mpcc_bottom = mpc1_get_mpcc(mpc, bot_mpcc_id); mpcc 423 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpcc->mpcc_bot = mpcc_bottom; mpcc 135 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h struct mpcc *mpc1_insert_plane( mpcc 140 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h struct mpcc *insert_above_mpcc, mpcc 147 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h struct mpcc *mpcc); mpcc 182 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h struct mpcc *mpc1_get_mpcc( mpcc 186 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h struct mpcc *mpc1_get_mpcc_for_dpp( mpcc 1730 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct mpcc *new_mpcc; mpcc 52 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); mpcc 68 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpcc->blnd_cfg = *blnd_cfg; mpcc 468 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst) mpcc 470 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpcc->mpcc_id = mpcc_inst; mpcc 471 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpcc->dpp_id = 0xf; mpcc 472 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpcc->mpcc_bot = NULL; mpcc 473 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpcc->blnd_cfg.overlap_only = false; mpcc 474 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpcc->blnd_cfg.global_alpha = 0xff; mpcc 475 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpcc->blnd_cfg.global_gain = 0xff; mpcc 476 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpcc->blnd_cfg.background_color_bpc = 4; mpcc 477 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpcc->blnd_cfg.bottom_gain_mode = 0; mpcc 478 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpcc->blnd_cfg.top_gain = 0x1f000; mpcc 479 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpcc->blnd_cfg.bottom_inside_gain = 0x1f000; mpcc 480 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpcc->blnd_cfg.bottom_outside_gain = 0x1f000; mpcc 481 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpcc->sm_cfg.enable = false; mpcc 484 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct mpcc *mpc2_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id) mpcc 486 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct mpcc *tmp_mpcc = tree->opp_list; mpcc 277 drivers/gpu/drm/amd/display/dc/inc/core_types.h uint32_t mpcc : 1; mpcc 111 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h struct mpcc *mpcc_bot; /* pointer to bottom layer MPCC. NULL when not connected */ mpcc 121 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h struct mpcc *opp_list; /* The top MPCC layer of the MPC tree that outputs to OPP endpoint */ mpcc 128 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h struct mpcc mpcc_array[MAX_MPCC]; mpcc 169 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h struct mpcc* (*insert_plane)( mpcc 174 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h struct mpcc *insert_above_mpcc, mpcc 191 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h struct mpcc *mpcc); mpcc 221 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h struct mpcc* (*get_mpcc_for_dpp)( mpcc 201 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h int mpcc[MAX_PIPES];