COM_OFF            18 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_BG_TIMER			COM_OFF(0x0C)
COM_OFF            19 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN		COM_OFF(0x34)
COM_OFF            20 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_SYS_CLK_CTRL		COM_OFF(0x3C)
COM_OFF            21 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_LOCK_CMP1_MODE0		COM_OFF(0x4C)
COM_OFF            22 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_LOCK_CMP2_MODE0		COM_OFF(0x50)
COM_OFF            23 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_LOCK_CMP3_MODE0		COM_OFF(0x54)
COM_OFF            24 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_LOCK_CMP1_MODE1		COM_OFF(0x58)
COM_OFF            25 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_LOCK_CMP2_MODE1		COM_OFF(0x5C)
COM_OFF            26 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_LOCK_CMP3_MODE1		COM_OFF(0x60)
COM_OFF            27 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_CP_CTRL_MODE0		COM_OFF(0x78)
COM_OFF            28 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_CP_CTRL_MODE1		COM_OFF(0x7C)
COM_OFF            29 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_PLL_RCTRL_MODE0		COM_OFF(0x84)
COM_OFF            30 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_PLL_RCTRL_MODE1		COM_OFF(0x88)
COM_OFF            31 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_PLL_CCTRL_MODE0		COM_OFF(0x90)
COM_OFF            32 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_PLL_CCTRL_MODE1		COM_OFF(0x94)
COM_OFF            33 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_SYSCLK_EN_SEL		COM_OFF(0xAC)
COM_OFF            34 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_RESETSM_CNTRL		COM_OFF(0xB4)
COM_OFF            35 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_LOCK_CMP_EN			COM_OFF(0xC8)
COM_OFF            36 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_LOCK_CMP_CFG		COM_OFF(0xCC)
COM_OFF            37 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_DEC_START_MODE0		COM_OFF(0xD0)
COM_OFF            38 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_DEC_START_MODE1		COM_OFF(0xD4)
COM_OFF            39 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_DIV_FRAC_START1_MODE0	COM_OFF(0xDC)
COM_OFF            40 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_DIV_FRAC_START2_MODE0	COM_OFF(0xE0)
COM_OFF            41 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_DIV_FRAC_START3_MODE0	COM_OFF(0xE4)
COM_OFF            42 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_DIV_FRAC_START1_MODE1	COM_OFF(0xE8)
COM_OFF            43 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_DIV_FRAC_START2_MODE1	COM_OFF(0xEC)
COM_OFF            44 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_DIV_FRAC_START3_MODE1	COM_OFF(0xF0)
COM_OFF            45 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0	COM_OFF(0x108)
COM_OFF            46 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0	COM_OFF(0x10C)
COM_OFF            47 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_INTEGLOOP_GAIN0_MODE1	COM_OFF(0x110)
COM_OFF            48 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_INTEGLOOP_GAIN1_MODE1	COM_OFF(0x114)
COM_OFF            49 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_VCO_TUNE_CTRL		COM_OFF(0x124)
COM_OFF            50 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_VCO_TUNE_MAP		COM_OFF(0x128)
COM_OFF            51 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_VCO_TUNE1_MODE0		COM_OFF(0x12C)
COM_OFF            52 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_VCO_TUNE2_MODE0		COM_OFF(0x130)
COM_OFF            53 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_VCO_TUNE1_MODE1		COM_OFF(0x134)
COM_OFF            54 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_VCO_TUNE2_MODE1		COM_OFF(0x138)
COM_OFF            55 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_VCO_TUNE_TIMER1		COM_OFF(0x144)
COM_OFF            56 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_VCO_TUNE_TIMER2		COM_OFF(0x148)
COM_OFF            57 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_CLK_SELECT			COM_OFF(0x174)
COM_OFF            58 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_HSCLK_SEL			COM_OFF(0x178)
COM_OFF            59 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_CORECLK_DIV			COM_OFF(0x184)
COM_OFF            60 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_CORE_CLK_EN			COM_OFF(0x18C)
COM_OFF            61 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_CMN_CONFIG			COM_OFF(0x194)
COM_OFF            62 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_SVS_MODE_CLK_SEL		COM_OFF(0x19C)
COM_OFF            63 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define QSERDES_COM_CORECLK_DIV_MODE1		COM_OFF(0x1BC)
COM_OFF            19 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_SYS_CLK_CTRL		COM_OFF(0x0)
COM_OFF            20 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_PLL_VCOTAIL_EN		COM_OFF(0x04)
COM_OFF            21 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_PLL_CNTRL			COM_OFF(0x14)
COM_OFF            22 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_PLL_IP_SETI			COM_OFF(0x24)
COM_OFF            23 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_CORE_CLK_IN_SYNC_SEL	COM_OFF(0x28)
COM_OFF            24 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN		COM_OFF(0x30)
COM_OFF            25 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_PLL_CP_SETI			COM_OFF(0x34)
COM_OFF            26 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_PLL_IP_SETP			COM_OFF(0x38)
COM_OFF            27 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_PLL_CP_SETP			COM_OFF(0x3C)
COM_OFF            28 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_SYSCLK_EN_SEL_TXBAND	COM_OFF(0x48)
COM_OFF            29 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_RESETSM_CNTRL		COM_OFF(0x4C)
COM_OFF            30 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_RESETSM_CNTRL2		COM_OFF(0x50)
COM_OFF            31 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_PLLLOCK_CMP1		COM_OFF(0x90)
COM_OFF            32 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_PLLLOCK_CMP2		COM_OFF(0x94)
COM_OFF            33 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_PLLLOCK_CMP3		COM_OFF(0x98)
COM_OFF            34 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_PLLLOCK_CMP_EN		COM_OFF(0x9C)
COM_OFF            35 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_BGTC			COM_OFF(0xA0)
COM_OFF            36 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_DEC_START1			COM_OFF(0xAC)
COM_OFF            37 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_PLL_AMP_OS			COM_OFF(0xB0)
COM_OFF            38 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_RES_CODE_UP_OFFSET		COM_OFF(0xD8)
COM_OFF            39 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_RES_CODE_DN_OFFSET		COM_OFF(0xDC)
COM_OFF            40 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_DIV_FRAC_START1		COM_OFF(0x100)
COM_OFF            41 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_DIV_FRAC_START2		COM_OFF(0x104)
COM_OFF            42 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_DIV_FRAC_START3		COM_OFF(0x108)
COM_OFF            43 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_DEC_START2			COM_OFF(0x10C)
COM_OFF            44 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_PLL_RXTXEPCLK_EN		COM_OFF(0x110)
COM_OFF            45 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_PLL_CRCTRL			COM_OFF(0x114)
COM_OFF            46 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define QSERDES_COM_PLL_CLKEPDIV		COM_OFF(0x118)