mm_pool32a_op 67 arch/mips/kernel/branch.c case mm_pool32a_op: mm_pool32a_op 305 arch/mips/kernel/process.c if (ip->r_format.opcode != mm_pool32a_op || mm_pool32a_op 1451 arch/mips/kernel/unaligned.c case mm_pool32a_op: mm_pool32a_op 43 arch/mips/mm/uasm-micromips.c [insn_addu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD}, mm_pool32a_op 45 arch/mips/mm/uasm-micromips.c [insn_and] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD}, mm_pool32a_op 61 arch/mips/mm/uasm-micromips.c [insn_di] = {M(mm_pool32a_op, 0, 0, 0, mm_di_op, mm_pool32axf_op), RS}, mm_pool32a_op 62 arch/mips/mm/uasm-micromips.c [insn_divu] = {M(mm_pool32a_op, 0, 0, 0, mm_divu_op, mm_pool32axf_op), RT | RS}, mm_pool32a_op 73 arch/mips/mm/uasm-micromips.c [insn_eret] = {M(mm_pool32a_op, 0, 0, 0, mm_eret_op, mm_pool32axf_op), 0}, mm_pool32a_op 74 arch/mips/mm/uasm-micromips.c [insn_ins] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE}, mm_pool32a_op 75 arch/mips/mm/uasm-micromips.c [insn_ext] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE}, mm_pool32a_op 78 arch/mips/mm/uasm-micromips.c [insn_jalr] = {M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RT | RS}, mm_pool32a_op 79 arch/mips/mm/uasm-micromips.c [insn_jr] = {M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RS}, mm_pool32a_op 87 arch/mips/mm/uasm-micromips.c [insn_mfc0] = {M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD}, mm_pool32a_op 88 arch/mips/mm/uasm-micromips.c [insn_mfhi] = {M(mm_pool32a_op, 0, 0, 0, mm_mfhi32_op, mm_pool32axf_op), RS}, mm_pool32a_op 89 arch/mips/mm/uasm-micromips.c [insn_mflo] = {M(mm_pool32a_op, 0, 0, 0, mm_mflo32_op, mm_pool32axf_op), RS}, mm_pool32a_op 90 arch/mips/mm/uasm-micromips.c [insn_mtc0] = {M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD}, mm_pool32a_op 91 arch/mips/mm/uasm-micromips.c [insn_mthi] = {M(mm_pool32a_op, 0, 0, 0, mm_mthi32_op, mm_pool32axf_op), RS}, mm_pool32a_op 92 arch/mips/mm/uasm-micromips.c [insn_mtlo] = {M(mm_pool32a_op, 0, 0, 0, mm_mtlo32_op, mm_pool32axf_op), RS}, mm_pool32a_op 93 arch/mips/mm/uasm-micromips.c [insn_mul] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD}, mm_pool32a_op 94 arch/mips/mm/uasm-micromips.c [insn_or] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD}, mm_pool32a_op 101 arch/mips/mm/uasm-micromips.c [insn_sll] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD}, mm_pool32a_op 102 arch/mips/mm/uasm-micromips.c [insn_sllv] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sllv32_op), RT | RS | RD}, mm_pool32a_op 103 arch/mips/mm/uasm-micromips.c [insn_slt] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_slt_op), RT | RS | RD}, mm_pool32a_op 105 arch/mips/mm/uasm-micromips.c [insn_sltu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sltu_op), RT | RS | RD}, mm_pool32a_op 106 arch/mips/mm/uasm-micromips.c [insn_sra] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD}, mm_pool32a_op 107 arch/mips/mm/uasm-micromips.c [insn_srav] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srav_op), RT | RS | RD}, mm_pool32a_op 108 arch/mips/mm/uasm-micromips.c [insn_srl] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD}, mm_pool32a_op 109 arch/mips/mm/uasm-micromips.c [insn_srlv] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srlv32_op), RT | RS | RD}, mm_pool32a_op 110 arch/mips/mm/uasm-micromips.c [insn_rotr] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD}, mm_pool32a_op 111 arch/mips/mm/uasm-micromips.c [insn_subu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD}, mm_pool32a_op 113 arch/mips/mm/uasm-micromips.c [insn_sync] = {M(mm_pool32a_op, 0, 0, 0, mm_sync_op, mm_pool32axf_op), RS}, mm_pool32a_op 114 arch/mips/mm/uasm-micromips.c [insn_tlbp] = {M(mm_pool32a_op, 0, 0, 0, mm_tlbp_op, mm_pool32axf_op), 0}, mm_pool32a_op 115 arch/mips/mm/uasm-micromips.c [insn_tlbr] = {M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0}, mm_pool32a_op 116 arch/mips/mm/uasm-micromips.c [insn_tlbwi] = {M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0}, mm_pool32a_op 117 arch/mips/mm/uasm-micromips.c [insn_tlbwr] = {M(mm_pool32a_op, 0, 0, 0, mm_tlbwr_op, mm_pool32axf_op), 0}, mm_pool32a_op 118 arch/mips/mm/uasm-micromips.c [insn_wait] = {M(mm_pool32a_op, 0, 0, 0, mm_wait_op, mm_pool32axf_op), SCIMM}, mm_pool32a_op 119 arch/mips/mm/uasm-micromips.c [insn_wsbh] = {M(mm_pool32a_op, 0, 0, 0, mm_wsbh_op, mm_pool32axf_op), RT | RS}, mm_pool32a_op 120 arch/mips/mm/uasm-micromips.c [insn_xor] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD}, mm_pool32a_op 124 arch/mips/mm/uasm-micromips.c [insn_syscall] = {M(mm_pool32a_op, 0, 0, 0, mm_syscall_op, mm_pool32axf_op), SCIMM},