mmVCE_UENC_REG_CLOCK_GATING  174 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c 	WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
mmVCE_UENC_REG_CLOCK_GATING  323 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c 		tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
mmVCE_UENC_REG_CLOCK_GATING  325 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c 		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
mmVCE_UENC_REG_CLOCK_GATING  339 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c 		tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
mmVCE_UENC_REG_CLOCK_GATING  341 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c 		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
mmVCE_UENC_REG_CLOCK_GATING  371 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c 	orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
mmVCE_UENC_REG_CLOCK_GATING  374 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c 		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
mmVCE_UENC_REG_CLOCK_GATING  377 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c 	WREG32(mmVCE_UENC_REG_CLOCK_GATING, 0x00);
mmVCE_UENC_REG_CLOCK_GATING  197 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c 		data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
mmVCE_UENC_REG_CLOCK_GATING  199 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c 		WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);
mmVCE_UENC_REG_CLOCK_GATING  221 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c 		data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
mmVCE_UENC_REG_CLOCK_GATING  223 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c 		WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);
mmVCE_UENC_REG_CLOCK_GATING  530 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c 	WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
mmVCE_UENC_REG_CLOCK_GATING  609 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), 0x3F, ~0x3F);
mmVCE_UENC_REG_CLOCK_GATING  836 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING));
mmVCE_UENC_REG_CLOCK_GATING  838 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), data);
mmVCE_UENC_REG_CLOCK_GATING  860 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING));
mmVCE_UENC_REG_CLOCK_GATING  862 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), data);