mmVCE_RB_WPTR3 126 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c v = RREG32(mmVCE_RB_WPTR3); mmVCE_RB_WPTR3 157 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr)); mmVCE_RB_WPTR3 296 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr)); mmVCE_RB_WPTR3 92 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3)); mmVCE_RB_WPTR3 120 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3), mmVCE_RB_WPTR3 359 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3), lower_32_bits(ring->wptr));