mmVCE_RB_WPTR2 79 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c return RREG32(mmVCE_RB_WPTR2); mmVCE_RB_WPTR2 96 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); mmVCE_RB_WPTR2 252 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); mmVCE_RB_WPTR2 124 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c v = RREG32(mmVCE_RB_WPTR2); mmVCE_RB_WPTR2 155 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); mmVCE_RB_WPTR2 289 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); mmVCE_RB_WPTR2 90 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2)); mmVCE_RB_WPTR2 117 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), mmVCE_RB_WPTR2 351 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), lower_32_bits(ring->wptr));