mmVCE_RB_WPTR      77 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c 		return RREG32(mmVCE_RB_WPTR);
mmVCE_RB_WPTR      94 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c 		WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
mmVCE_RB_WPTR     245 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c 	WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
mmVCE_RB_WPTR     122 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c 		v = RREG32(mmVCE_RB_WPTR);
mmVCE_RB_WPTR     153 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c 		WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
mmVCE_RB_WPTR     282 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c 			WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
mmVCE_RB_WPTR      88 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR));
mmVCE_RB_WPTR     114 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR),
mmVCE_RB_WPTR     343 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), lower_32_bits(ring->wptr));