mmVCE_RB_BASE_HI  247 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c 	WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
mmVCE_RB_BASE_HI  284 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c 			WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
mmVCE_RB_BASE_HI  235 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI),
mmVCE_RB_BASE_HI  345 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), upper_32_bits(ring->gpu_addr));