mmUVD_VCPU_CNTL   275 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 	WREG32(mmUVD_VCPU_CNTL,  1 << 9);
mmUVD_VCPU_CNTL   426 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 	WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9));
mmUVD_VCPU_CNTL   352 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	WREG32(mmUVD_VCPU_CNTL,  1 << 9);
mmUVD_VCPU_CNTL   447 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	WREG32(mmUVD_VCPU_CNTL, 0x0);
mmUVD_VCPU_CNTL   768 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
mmUVD_VCPU_CNTL   880 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	WREG32(mmUVD_VCPU_CNTL, 0x0);
mmUVD_VCPU_CNTL   881 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
mmUVD_VCPU_CNTL  1012 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL,
mmUVD_VCPU_CNTL  1139 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0);
mmUVD_VCPU_CNTL   847 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
mmUVD_VCPU_CNTL   995 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0);
mmUVD_VCPU_CNTL  1161 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
mmUVD_VCPU_CNTL   952 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 		UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
mmUVD_VCPU_CNTL  1081 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
mmUVD_VCPU_CNTL  1300 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
mmUVD_VCPU_CNTL   736 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
mmUVD_VCPU_CNTL   798 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0,
mmUVD_VCPU_CNTL   818 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 			WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
mmUVD_VCPU_CNTL   822 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 			WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0,
mmUVD_VCPU_CNTL   928 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
mmUVD_VCPU_CNTL   933 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0,