mmUVD_VCPU_CACHE_OFFSET2  560 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 	WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);
mmUVD_VCPU_CACHE_OFFSET2  277 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
mmUVD_VCPU_CACHE_OFFSET2  603 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
mmUVD_VCPU_CACHE_OFFSET2  693 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21));
mmUVD_VCPU_CACHE_OFFSET2  836 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));
mmUVD_VCPU_CACHE_OFFSET2  332 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
mmUVD_VCPU_CACHE_OFFSET2  406 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0);
mmUVD_VCPU_CACHE_OFFSET2  401 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
mmUVD_VCPU_CACHE_OFFSET2  482 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 		UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
mmUVD_VCPU_CACHE_OFFSET2  417 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, 0);