mmUVD_STATUS      215 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 	if (RREG32(mmUVD_STATUS) != 0)
mmUVD_STATUS      265 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 	WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2));
mmUVD_STATUS      319 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 			status = RREG32(mmUVD_STATUS);
mmUVD_STATUS      345 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 	WREG32_P(mmUVD_STATUS, 0, ~(1<<2));
mmUVD_STATUS      390 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 			status = RREG32(mmUVD_STATUS);
mmUVD_STATUS      433 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 	WREG32(mmUVD_STATUS, 0);
mmUVD_STATUS      213 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	if (RREG32(mmUVD_STATUS) != 0)
mmUVD_STATUS      364 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 			status = RREG32(mmUVD_STATUS);
mmUVD_STATUS      390 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	WREG32_P(mmUVD_STATUS, 0, ~(2 << 1));
mmUVD_STATUS      452 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	WREG32(mmUVD_STATUS, 0);
mmUVD_STATUS      540 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	if (RREG32(mmUVD_STATUS) != 0)
mmUVD_STATUS      781 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 			status = RREG32(mmUVD_STATUS);
mmUVD_STATUS      808 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
mmUVD_STATUS      885 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	WREG32(mmUVD_STATUS, 0);
mmUVD_STATUS     1141 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	    (RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK))
mmUVD_STATUS      800 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
mmUVD_STATUS      890 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
mmUVD_STATUS      912 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02);
mmUVD_STATUS     1027 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 				status = RREG32_SOC15(UVD, k, mmUVD_STATUS);
mmUVD_STATUS     1057 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0,
mmUVD_STATUS     1462 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 	    (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) &
mmUVD_STATUS      237 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		RREG32_SOC15(VCN, 0, mmUVD_STATUS))
mmUVD_STATUS      794 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
mmUVD_STATUS      795 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
mmUVD_STATUS      866 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 			status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
mmUVD_STATUS      900 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY;
mmUVD_STATUS      901 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
mmUVD_STATUS     1143 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, ret_code);
mmUVD_STATUS     1173 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);
mmUVD_STATUS     1356 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
mmUVD_STATUS     1364 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
mmUVD_STATUS      298 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	      RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
mmUVD_STATUS     1074 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
mmUVD_STATUS     1075 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
mmUVD_STATUS     1149 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 			status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
mmUVD_STATUS     1180 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
mmUVD_STATUS     1276 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
mmUVD_STATUS     1319 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
mmUVD_STATUS     1397 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
mmUVD_STATUS     1405 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
mmUVD_STATUS      310 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		if (RREG32_SOC15(VCN, i, mmUVD_STATUS))
mmUVD_STATUS      725 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		tmp = RREG32_SOC15(UVD, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
mmUVD_STATUS      726 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_SOC15(UVD, i, mmUVD_STATUS, tmp);
mmUVD_STATUS      805 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 				status = RREG32_SOC15(UVD, i, mmUVD_STATUS);
mmUVD_STATUS      840 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0,
mmUVD_STATUS      899 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
mmUVD_STATUS      937 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);
mmUVD_STATUS     1258 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);
mmUVD_STATUS     1272 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,