mmUVD_RB_WPTR     126 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 		return RREG32(mmUVD_RB_WPTR);
mmUVD_RB_WPTR     157 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 		WREG32(mmUVD_RB_WPTR,
mmUVD_RB_WPTR     843 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 		WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
mmUVD_RB_WPTR     124 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR);
mmUVD_RB_WPTR     162 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR,
mmUVD_RB_WPTR    1095 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
mmUVD_RB_WPTR     939 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
mmUVD_RB_WPTR    1191 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
mmUVD_RB_WPTR    1265 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 				WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
mmUVD_RB_WPTR    1619 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
mmUVD_RB_WPTR    1636 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
mmUVD_RB_WPTR    1209 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
mmUVD_RB_WPTR    1237 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
mmUVD_RB_WPTR    1366 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 				WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
mmUVD_RB_WPTR    1681 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 			return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
mmUVD_RB_WPTR    1706 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 			WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
mmUVD_RB_WPTR     869 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_SOC15(UVD, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
mmUVD_RB_WPTR    1062 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 			return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR);
mmUVD_RB_WPTR    1087 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 			WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));