mmUVD_RBC_RB_WPTR   76 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 	return RREG32(mmUVD_RBC_RB_WPTR);
mmUVD_RBC_RB_WPTR   90 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
mmUVD_RBC_RB_WPTR  361 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
mmUVD_RBC_RB_WPTR   74 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	return RREG32(mmUVD_RBC_RB_WPTR);
mmUVD_RBC_RB_WPTR   88 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
mmUVD_RBC_RB_WPTR  419 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
mmUVD_RBC_RB_WPTR  111 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	return RREG32(mmUVD_RBC_RB_WPTR);
mmUVD_RBC_RB_WPTR  142 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
mmUVD_RBC_RB_WPTR  836 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
mmUVD_RBC_RB_WPTR  106 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 	return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);
mmUVD_RBC_RB_WPTR  140 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 	WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
mmUVD_RBC_RB_WPTR 1087 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR,
mmUVD_RBC_RB_WPTR  931 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
mmUVD_RBC_RB_WPTR 1104 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
mmUVD_RBC_RB_WPTR 1200 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
mmUVD_RBC_RB_WPTR 1275 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 				WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
mmUVD_RBC_RB_WPTR 1335 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 				WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
mmUVD_RBC_RB_WPTR 1413 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
mmUVD_RBC_RB_WPTR 1431 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
mmUVD_RBC_RB_WPTR 1048 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
mmUVD_RBC_RB_WPTR 1204 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
mmUVD_RBC_RB_WPTR 1246 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
mmUVD_RBC_RB_WPTR 1375 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 				WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
mmUVD_RBC_RB_WPTR 1457 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 		return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
mmUVD_RBC_RB_WPTR 1479 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 		WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
mmUVD_RBC_RB_WPTR  865 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_SOC15(UVD, i, mmUVD_RBC_RB_WPTR,
mmUVD_RBC_RB_WPTR  978 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);
mmUVD_RBC_RB_WPTR  996 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));