mmUVD_RBC_RB_RPTR   62 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 	return RREG32(mmUVD_RBC_RB_RPTR);
mmUVD_RBC_RB_RPTR  358 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 	WREG32(mmUVD_RBC_RB_RPTR, 0x0);
mmUVD_RBC_RB_RPTR  360 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 	ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
mmUVD_RBC_RB_RPTR   60 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	return RREG32(mmUVD_RBC_RB_RPTR);
mmUVD_RBC_RB_RPTR  416 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	WREG32(mmUVD_RBC_RB_RPTR, 0);
mmUVD_RBC_RB_RPTR  418 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
mmUVD_RBC_RB_RPTR   81 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	return RREG32(mmUVD_RBC_RB_RPTR);
mmUVD_RBC_RB_RPTR  833 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	WREG32(mmUVD_RBC_RB_RPTR, 0);
mmUVD_RBC_RB_RPTR  835 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
mmUVD_RBC_RB_RPTR   75 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 	return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);
mmUVD_RBC_RB_RPTR 1084 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0);
mmUVD_RBC_RB_RPTR 1086 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR);
mmUVD_RBC_RB_RPTR  926 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
mmUVD_RBC_RB_RPTR  930 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
mmUVD_RBC_RB_RPTR 1099 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
mmUVD_RBC_RB_RPTR 1103 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
mmUVD_RBC_RB_RPTR 1201 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
mmUVD_RBC_RB_RPTR 1399 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
mmUVD_RBC_RB_RPTR 1043 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
mmUVD_RBC_RB_RPTR 1047 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
mmUVD_RBC_RB_RPTR 1201 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
mmUVD_RBC_RB_RPTR 1203 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
mmUVD_RBC_RB_RPTR 1247 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
mmUVD_RBC_RB_RPTR 1440 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
mmUVD_RBC_RB_RPTR  862 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_SOC15(UVD, i, mmUVD_RBC_RB_RPTR, 0);
mmUVD_RBC_RB_RPTR  864 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		ring->wptr = RREG32_SOC15(UVD, i, mmUVD_RBC_RB_RPTR);
mmUVD_RBC_RB_RPTR  961 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 	return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);