mmUVD_RBC_RB_CNTL  348 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 	WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
mmUVD_RBC_RB_CNTL  369 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 	WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);
mmUVD_RBC_RB_CNTL  386 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 	WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
mmUVD_RBC_RB_CNTL  401 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	WREG32(mmUVD_RBC_RB_CNTL, tmp);
mmUVD_RBC_RB_CNTL  421 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
mmUVD_RBC_RB_CNTL  436 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
mmUVD_RBC_RB_CNTL  818 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	WREG32(mmUVD_RBC_RB_CNTL, tmp);
mmUVD_RBC_RB_CNTL  869 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
mmUVD_RBC_RB_CNTL  897 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
mmUVD_RBC_RB_CNTL 1068 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp);
mmUVD_RBC_RB_CNTL 1090 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0,
mmUVD_RBC_RB_CNTL 1125 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101);
mmUVD_RBC_RB_CNTL  910 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
mmUVD_RBC_RB_CNTL  934 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
mmUVD_RBC_RB_CNTL 1083 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
mmUVD_RBC_RB_CNTL 1107 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
mmUVD_RBC_RB_CNTL 1027 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
mmUVD_RBC_RB_CNTL 1192 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
mmUVD_RBC_RB_CNTL  853 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, tmp);