mmUVD_POWER_STATUS 301 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); mmUVD_POWER_STATUS 708 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); mmUVD_POWER_STATUS 1454 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); mmUVD_POWER_STATUS 942 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0, mmUVD_POWER_STATUS 1734 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); mmUVD_POWER_STATUS 725 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); mmUVD_POWER_STATUS 730 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); mmUVD_POWER_STATUS 740 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); mmUVD_POWER_STATUS 743 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); mmUVD_POWER_STATUS 983 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); mmUVD_POWER_STATUS 986 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); mmUVD_POWER_STATUS 1186 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, mmUVD_POWER_STATUS 1203 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, mmUVD_POWER_STATUS 1208 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, mmUVD_POWER_STATUS 1247 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, mmUVD_POWER_STATUS 1277 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, mmUVD_POWER_STATUS 1302 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, mmUVD_POWER_STATUS 1308 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); mmUVD_POWER_STATUS 1310 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2); mmUVD_POWER_STATUS 1337 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, mmUVD_POWER_STATUS 879 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); mmUVD_POWER_STATUS 885 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); mmUVD_POWER_STATUS 895 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); mmUVD_POWER_STATUS 898 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); mmUVD_POWER_STATUS 936 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); mmUVD_POWER_STATUS 939 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); mmUVD_POWER_STATUS 1233 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, mmUVD_POWER_STATUS 1249 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, mmUVD_POWER_STATUS 1253 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, mmUVD_POWER_STATUS 1347 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1, mmUVD_POWER_STATUS 1378 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, mmUVD_POWER_STATUS 721 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS), 0, mmUVD_POWER_STATUS 942 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS),