mmUVD_MASTINT_EN  278 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 	WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
mmUVD_MASTINT_EN  343 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 	WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1));
mmUVD_MASTINT_EN  310 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
mmUVD_MASTINT_EN  387 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1));
mmUVD_MASTINT_EN  803 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	WREG32_P(mmUVD_MASTINT_EN,
mmUVD_MASTINT_EN  848 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
mmUVD_MASTINT_EN  885 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
mmUVD_MASTINT_EN  961 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0,
mmUVD_MASTINT_EN 1052 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN),
mmUVD_MASTINT_EN  801 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
mmUVD_MASTINT_EN  891 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
mmUVD_MASTINT_EN  998 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
mmUVD_MASTINT_EN 1052 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
mmUVD_MASTINT_EN  956 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 		UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
mmUVD_MASTINT_EN 1012 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 		UVD, 0, mmUVD_MASTINT_EN),
mmUVD_MASTINT_EN 1085 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
mmUVD_MASTINT_EN 1175 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
mmUVD_MASTINT_EN  740 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 0,
mmUVD_MASTINT_EN  835 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),