mmUVD_LMI_CTRL2   306 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 	WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
mmUVD_LMI_CTRL2   411 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 	WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
mmUVD_LMI_CTRL2   313 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
mmUVD_LMI_CTRL2   355 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
mmUVD_LMI_CTRL2   439 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
mmUVD_LMI_CTRL2   450 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
mmUVD_LMI_CTRL2   872 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
mmUVD_LMI_CTRL2   883 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
mmUVD_LMI_CTRL2   852 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
mmUVD_LMI_CTRL2   909 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
mmUVD_LMI_CTRL2   965 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2),
mmUVD_LMI_CTRL2  1016 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0,
mmUVD_LMI_CTRL2  1128 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
mmUVD_LMI_CTRL2  1142 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0,
mmUVD_LMI_CTRL2   854 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
mmUVD_LMI_CTRL2  1047 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2,
mmUVD_LMI_CTRL2  1007 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 		UVD, 0, mmUVD_LMI_CTRL2),
mmUVD_LMI_CTRL2  1129 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
mmUVD_LMI_CTRL2  1289 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2);
mmUVD_LMI_CTRL2  1291 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp);
mmUVD_LMI_CTRL2   791 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0,
mmUVD_LMI_CTRL2   912 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);
mmUVD_LMI_CTRL2   914 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);