mmUVD_JRBC_RB_WPTR  958 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
mmUVD_JRBC_RB_WPTR  962 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
mmUVD_JRBC_RB_WPTR 1112 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
mmUVD_JRBC_RB_WPTR 1197 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
mmUVD_JRBC_RB_WPTR 1330 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 				WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr);
mmUVD_JRBC_RB_WPTR 1746 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
mmUVD_JRBC_RB_WPTR 1760 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
mmUVD_JRBC_RB_WPTR  720 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
mmUVD_JRBC_RB_WPTR  723 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
mmUVD_JRBC_RB_WPTR 1243 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
mmUVD_JRBC_RB_WPTR 1821 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 		return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
mmUVD_JRBC_RB_WPTR 1839 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 		WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
mmUVD_JRBC_RB_WPTR  666 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_WPTR, 0);
mmUVD_JRBC_RB_WPTR  669 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		ring->wptr = RREG32_SOC15(UVD, i, mmUVD_JRBC_RB_WPTR);
mmUVD_JRBC_RB_WPTR 1157 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		return RREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_WPTR);
mmUVD_JRBC_RB_WPTR 1175 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));