mmUVD_JRBC_RB_RPTR  957 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);
mmUVD_JRBC_RB_RPTR 1198 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
mmUVD_JRBC_RB_RPTR 1329 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 				WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr);
mmUVD_JRBC_RB_RPTR 1732 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR);
mmUVD_JRBC_RB_RPTR 2091 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_RPTR);
mmUVD_JRBC_RB_RPTR  719 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);
mmUVD_JRBC_RB_RPTR 1244 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
mmUVD_JRBC_RB_RPTR 1804 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR);
mmUVD_JRBC_RB_RPTR  665 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_RPTR, 0);
mmUVD_JRBC_RB_RPTR 1140 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 	return RREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_RPTR);