mmUVD_JRBC_RB_CNTL  953 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
mmUVD_JRBC_RB_CNTL  959 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
mmUVD_JRBC_RB_CNTL 1322 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 				WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
mmUVD_JRBC_RB_CNTL 1331 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 				WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
mmUVD_JRBC_RB_CNTL 2052 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
mmUVD_JRBC_RB_CNTL 2064 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
mmUVD_JRBC_RB_CNTL 2097 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
mmUVD_JRBC_RB_CNTL  714 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
mmUVD_JRBC_RB_CNTL  721 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
mmUVD_JRBC_RB_CNTL  660 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
mmUVD_JRBC_RB_CNTL  667 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_CNTL, 0x00000002L);