mmSDMA0_STATUS_REG  169 drivers/gpu/drm/amd/amdgpu/nv.c 	{ SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
mmSDMA0_STATUS_REG 1950 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 		u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG);
mmSDMA0_STATUS_REG 1967 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 			sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG);
mmSDMA0_STATUS_REG 1327 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
mmSDMA0_STATUS_REG 1343 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
mmSDMA0_STATUS_REG 1344 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
mmSDMA0_STATUS_REG  356 drivers/gpu/drm/amd/amdgpu/soc15.c 	{ SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
mmSDMA0_STATUS_REG  482 drivers/gpu/drm/amd/amdgpu/vi.c 	{mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
mmSDMA0_STATUS_REG  483 drivers/gpu/drm/amd/amdgpu/vi.c 	{mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},