mmSDMA0_GFX_RB_WPTR_HI  569 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 		wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI);
mmSDMA0_GFX_RB_WPTR_HI  616 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 		WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI,
mmSDMA0_GFX_RB_WPTR_HI 1002 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0);
mmSDMA0_GFX_RB_WPTR_HI  303 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		highbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
mmSDMA0_GFX_RB_WPTR_HI  351 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
mmSDMA0_GFX_RB_WPTR_HI  655 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
mmSDMA0_GFX_RB_WPTR_HI  689 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);