mmSDMA0_GFX_RB_WPTR 183 drivers/gpu/drm/amd/amdgpu/cik_sdma.c return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2; mmSDMA0_GFX_RB_WPTR 197 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], mmSDMA0_GFX_RB_WPTR 472 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); mmSDMA0_GFX_RB_WPTR 488 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); mmSDMA0_GFX_RB_WPTR 210 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; mmSDMA0_GFX_RB_WPTR 226 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); mmSDMA0_GFX_RB_WPTR 450 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); mmSDMA0_GFX_RB_WPTR 466 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); mmSDMA0_GFX_RB_WPTR 372 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; mmSDMA0_GFX_RB_WPTR 399 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); mmSDMA0_GFX_RB_WPTR 725 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); mmSDMA0_GFX_RB_WPTR 571 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); mmSDMA0_GFX_RB_WPTR 614 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR, mmSDMA0_GFX_RB_WPTR 1001 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0); mmSDMA0_GFX_RB_WPTR 302 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c lowbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2; mmSDMA0_GFX_RB_WPTR 349 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), mmSDMA0_GFX_RB_WPTR 654 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); mmSDMA0_GFX_RB_WPTR 688 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);