mmPIPE0_DMIF_BUFFER_CONTROL  626 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
mmPIPE0_DMIF_BUFFER_CONTROL  628 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
mmPIPE0_DMIF_BUFFER_CONTROL  631 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
mmPIPE0_DMIF_BUFFER_CONTROL  652 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
mmPIPE0_DMIF_BUFFER_CONTROL  654 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
mmPIPE0_DMIF_BUFFER_CONTROL  657 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
mmPIPE0_DMIF_BUFFER_CONTROL 1020 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
mmPIPE0_DMIF_BUFFER_CONTROL 1023 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
mmPIPE0_DMIF_BUFFER_CONTROL  563 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
mmPIPE0_DMIF_BUFFER_CONTROL  566 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &