mmMP1_SMN_C2PMSG_90   78 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
mmMP1_SMN_C2PMSG_90   88 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
mmMP1_SMN_C2PMSG_90  102 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
mmMP1_SMN_C2PMSG_90  133 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
mmMP1_SMN_C2PMSG_90   67 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 		cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
mmMP1_SMN_C2PMSG_90   77 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
mmMP1_SMN_C2PMSG_90   91 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
mmMP1_SMN_C2PMSG_90  121 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
mmMP1_SMN_C2PMSG_90   54 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
mmMP1_SMN_C2PMSG_90   59 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
mmMP1_SMN_C2PMSG_90   85 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
mmMP1_SMN_C2PMSG_90  103 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
mmMP1_SMN_C2PMSG_90   64 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
mmMP1_SMN_C2PMSG_90   72 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
mmMP1_SMN_C2PMSG_90  104 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
mmMP1_SMN_C2PMSG_90  130 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
mmMP1_SMN_C2PMSG_90   73 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
mmMP1_SMN_C2PMSG_90   78 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
mmMP1_SMN_C2PMSG_90  110 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
mmMP1_SMN_C2PMSG_90  136 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);