mmIH_RB_WPTR       90 drivers/gpu/drm/amd/amdgpu/cik_ih.c 	WREG32(mmIH_RB_WPTR, 0);
mmIH_RB_WPTR      143 drivers/gpu/drm/amd/amdgpu/cik_ih.c 	WREG32(mmIH_RB_WPTR, 0);
mmIH_RB_WPTR       90 drivers/gpu/drm/amd/amdgpu/cz_ih.c 	WREG32(mmIH_RB_WPTR, 0);
mmIH_RB_WPTR      145 drivers/gpu/drm/amd/amdgpu/cz_ih.c 	WREG32(mmIH_RB_WPTR, 0);
mmIH_RB_WPTR       90 drivers/gpu/drm/amd/amdgpu/iceland_ih.c 	WREG32(mmIH_RB_WPTR, 0);
mmIH_RB_WPTR      145 drivers/gpu/drm/amd/amdgpu/iceland_ih.c 	WREG32(mmIH_RB_WPTR, 0);
mmIH_RB_WPTR       71 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
mmIH_RB_WPTR      150 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
mmIH_RB_WPTR      220 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
mmIH_RB_WPTR       86 drivers/gpu/drm/amd/amdgpu/tonga_ih.c 	WREG32(mmIH_RB_WPTR, 0);
mmIH_RB_WPTR      143 drivers/gpu/drm/amd/amdgpu/tonga_ih.c 	WREG32(mmIH_RB_WPTR, 0);
mmIH_RB_WPTR      120 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
mmIH_RB_WPTR      268 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
mmIH_RB_WPTR      386 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);