mmGB_TILE_MODE0   971 drivers/gpu/drm/amd/amdgpu/cik.c 	{mmGB_TILE_MODE0},
mmGB_TILE_MODE0  1065 drivers/gpu/drm/amd/amdgpu/cik.c 		case mmGB_TILE_MODE0:
mmGB_TILE_MODE0  1097 drivers/gpu/drm/amd/amdgpu/cik.c 			idx = (reg_offset - mmGB_TILE_MODE0);
mmGB_TILE_MODE0   641 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 			WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
mmGB_TILE_MODE0   847 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 			WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
mmGB_TILE_MODE0  1071 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 			WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
mmGB_TILE_MODE0  1295 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 			WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
mmGB_TILE_MODE0  1216 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 			WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
mmGB_TILE_MODE0  1399 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 			WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
mmGB_TILE_MODE0  1569 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 			WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
mmGB_TILE_MODE0  2306 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 				WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
mmGB_TILE_MODE0  2496 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 			WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
mmGB_TILE_MODE0  2685 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 			WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
mmGB_TILE_MODE0  2888 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 			WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
mmGB_TILE_MODE0  3090 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 			WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
mmGB_TILE_MODE0  3261 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 				WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
mmGB_TILE_MODE0  3438 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 				WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
mmGB_TILE_MODE0  1053 drivers/gpu/drm/amd/amdgpu/si.c 		case mmGB_TILE_MODE0:
mmGB_TILE_MODE0  1085 drivers/gpu/drm/amd/amdgpu/si.c 			idx = (reg_offset - mmGB_TILE_MODE0);
mmGB_TILE_MODE0   496 drivers/gpu/drm/amd/amdgpu/vi.c 	{mmGB_TILE_MODE0},
mmGB_TILE_MODE0   589 drivers/gpu/drm/amd/amdgpu/vi.c 		case mmGB_TILE_MODE0:
mmGB_TILE_MODE0   621 drivers/gpu/drm/amd/amdgpu/vi.c 			idx = (reg_offset - mmGB_TILE_MODE0);