mmDPG_PIPE_URGENCY_CONTROL 1122 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
mmDPG_PIPE_URGENCY_CONTROL 1125 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
mmDPG_PIPE_URGENCY_CONTROL 1129 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
mmDPG_PIPE_URGENCY_CONTROL 1132 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
mmDPG_PIPE_URGENCY_CONTROL 1148 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
mmDPG_PIPE_URGENCY_CONTROL 1151 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
mmDPG_PIPE_URGENCY_CONTROL 1155 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
mmDPG_PIPE_URGENCY_CONTROL 1158 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
mmDPG_PIPE_URGENCY_CONTROL  957 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
mmDPG_PIPE_URGENCY_CONTROL  965 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
mmDPG_PIPE_URGENCY_CONTROL 1059 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
mmDPG_PIPE_URGENCY_CONTROL 1067 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,