mmDC_HPD1_INT_CONTROL 264 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); mmDC_HPD1_INT_CONTROL 269 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); mmDC_HPD1_INT_CONTROL 303 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); mmDC_HPD1_INT_CONTROL 305 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); mmDC_HPD1_INT_CONTROL 2864 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); mmDC_HPD1_INT_CONTROL 2866 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); mmDC_HPD1_INT_CONTROL 2869 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); mmDC_HPD1_INT_CONTROL 2871 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); mmDC_HPD1_INT_CONTROL 3058 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); mmDC_HPD1_INT_CONTROL 3060 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); mmDC_HPD1_INT_CONTROL 258 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); mmDC_HPD1_INT_CONTROL 263 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); mmDC_HPD1_INT_CONTROL 297 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); mmDC_HPD1_INT_CONTROL 299 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); mmDC_HPD1_INT_CONTROL 2956 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); mmDC_HPD1_INT_CONTROL 2958 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); mmDC_HPD1_INT_CONTROL 2961 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); mmDC_HPD1_INT_CONTROL 2963 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); mmDC_HPD1_INT_CONTROL 3150 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); mmDC_HPD1_INT_CONTROL 3152 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);