mmD1VGA_CONTROL   902 drivers/gpu/drm/amd/amdgpu/cik.c 		d1vga_control = RREG32(mmD1VGA_CONTROL);
mmD1VGA_CONTROL   912 drivers/gpu/drm/amd/amdgpu/cik.c 		WREG32(mmD1VGA_CONTROL,
mmD1VGA_CONTROL   928 drivers/gpu/drm/amd/amdgpu/cik.c 		WREG32(mmD1VGA_CONTROL, d1vga_control);
mmD1VGA_CONTROL  1795 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	mmD1VGA_CONTROL,
mmD1VGA_CONTROL  1837 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	mmD1VGA_CONTROL,
mmD1VGA_CONTROL  1759 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	mmD1VGA_CONTROL,
mmD1VGA_CONTROL  1724 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	mmD1VGA_CONTROL,
mmD1VGA_CONTROL   666 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 	u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
mmD1VGA_CONTROL   822 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 	u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
mmD1VGA_CONTROL   942 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
mmD1VGA_CONTROL  1060 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
mmD1VGA_CONTROL  1148 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 	d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
mmD1VGA_CONTROL   386 drivers/gpu/drm/amd/amdgpu/vi.c 		d1vga_control = RREG32(mmD1VGA_CONTROL);
mmD1VGA_CONTROL   396 drivers/gpu/drm/amd/amdgpu/vi.c 		WREG32(mmD1VGA_CONTROL,
mmD1VGA_CONTROL   412 drivers/gpu/drm/amd/amdgpu/vi.c 		WREG32(mmD1VGA_CONTROL, d1vga_control);
mmD1VGA_CONTROL  1807 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c 		addr = mmD1VGA_CONTROL;
mmD1VGA_CONTROL   398 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		offset = mmD2VGA_CONTROL - mmD1VGA_CONTROL;
mmD1VGA_CONTROL   401 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		offset = mmD3VGA_CONTROL - mmD1VGA_CONTROL;
mmD1VGA_CONTROL   404 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		offset = mmD4VGA_CONTROL - mmD1VGA_CONTROL;
mmD1VGA_CONTROL   407 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		offset = mmD5VGA_CONTROL - mmD1VGA_CONTROL;
mmD1VGA_CONTROL   410 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		offset = mmD6VGA_CONTROL - mmD1VGA_CONTROL;
mmD1VGA_CONTROL   416 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	value = dm_read_reg_soc15(tg->ctx, mmD1VGA_CONTROL, offset);
mmD1VGA_CONTROL   424 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	dm_write_reg_soc15(tg->ctx, mmD1VGA_CONTROL, offset, value);