mmCRTC_MASTER_UPDATE_MODE 2101 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
mmCRTC_MASTER_UPDATE_MODE  230 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
mmCRTC_MASTER_UPDATE_MODE  140 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c 	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value);
mmCRTC_MASTER_UPDATE_MODE 1701 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c 	value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE));
mmCRTC_MASTER_UPDATE_MODE 1708 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c 	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value);
mmCRTC_MASTER_UPDATE_MODE  142 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c 			HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),