mmCRTC0_CRTC_TEST_PATTERN_CONTROL 1070 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_CONTROL, tg110->offsets.crtc, 0);
mmCRTC0_CRTC_TEST_PATTERN_CONTROL 1082 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_CONTROL, tg110->offsets.crtc,  value);