mmCP_MQD_BASE_ADDR  389 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
mmCP_MQD_BASE_ADDR  474 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
mmCP_MQD_BASE_ADDR  346 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 	for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++)
mmCP_MQD_BASE_ADDR  347 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 		WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
mmCP_MQD_BASE_ADDR  399 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 	for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++)
mmCP_MQD_BASE_ADDR  317 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 	for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++)
mmCP_MQD_BASE_ADDR  318 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 		WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
mmCP_MQD_BASE_ADDR  332 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 		WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
mmCP_MQD_BASE_ADDR  384 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 	for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_DONES; reg++)
mmCP_MQD_BASE_ADDR  290 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
mmCP_MQD_BASE_ADDR  374 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
mmCP_MQD_BASE_ADDR 3116 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
mmCP_MQD_BASE_ADDR 3433 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
mmCP_MQD_BASE_ADDR 3064 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
mmCP_MQD_BASE_ADDR 3067 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)
mmCP_MQD_BASE_ADDR 3068 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
mmCP_MQD_BASE_ADDR 4614 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
mmCP_MQD_BASE_ADDR 4628 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
mmCP_MQD_BASE_ADDR 4631 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)
mmCP_MQD_BASE_ADDR 4632 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
mmCP_MQD_BASE_ADDR 3593 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR,
mmCP_MQD_BASE_ADDR 1505 drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h 	{ 0x54116f00, mmCP_MQD_BASE_ADDR                         },
mmCP_MQD_BASE_ADDR 1515 drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h 	{ 0x54117300, mmCP_MQD_BASE_ADDR                         },
mmCP_MQD_BASE_ADDR 1525 drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h 	{ 0x54117700, mmCP_MQD_BASE_ADDR                         },
mmCP_MQD_BASE_ADDR 1535 drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h 	{ 0x54117b00, mmCP_MQD_BASE_ADDR                         },