mmCP_MEC_ME1_UCODE_DATA 2991 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
mmCP_MEC_ME1_UCODE_DATA 2747 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
mmCP_MEC_ME1_UCODE_DATA 3317 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
mmCP_MEC_ME1_UCODE_DATA  278 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
mmCP_MEC_ME1_UCODE_DATA  602 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
mmCP_MEC_ME1_UCODE_DATA  432 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
mmCP_MEC_ME1_UCODE_DATA  510 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);