mmCG_FDO_CTRL2 134 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), mmCG_FDO_CTRL2 137 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), mmCG_FDO_CTRL2 142 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, mmCG_FDO_CTRL2 143 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), mmCG_FDO_CTRL2 145 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, mmCG_FDO_CTRL2 146 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), mmCG_FDO_CTRL2 162 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, mmCG_FDO_CTRL2 163 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), mmCG_FDO_CTRL2 166 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, mmCG_FDO_CTRL2 167 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), mmCG_FDO_CTRL2 413 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, mmCG_FDO_CTRL2 414 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), mmCG_FDO_CTRL2 94 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, mmCG_FDO_CTRL2 95 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), mmCG_FDO_CTRL2 97 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, mmCG_FDO_CTRL2 98 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), mmCG_FDO_CTRL2 1412 drivers/gpu/drm/amd/powerplay/smu_v11_0.c WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, mmCG_FDO_CTRL2 1413 drivers/gpu/drm/amd/powerplay/smu_v11_0.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), mmCG_FDO_CTRL2 1415 drivers/gpu/drm/amd/powerplay/smu_v11_0.c WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, mmCG_FDO_CTRL2 1416 drivers/gpu/drm/amd/powerplay/smu_v11_0.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),