mmBIF_BX_PF0_MAILBOX_CONTROL 63 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h #define AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4 mmBIF_BX_PF0_MAILBOX_CONTROL 64 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h #define AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4 + 1