mmAZALIA_F0_CODEC_ENDPOINT_INDEX 181 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); mmAZALIA_F0_CODEC_ENDPOINT_INDEX 194 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); mmAZALIA_F0_CODEC_ENDPOINT_INDEX 199 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); mmAZALIA_F0_CODEC_ENDPOINT_INDEX 212 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); mmAZALIA_F0_CODEC_ENDPOINT_INDEX 132 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); mmAZALIA_F0_CODEC_ENDPOINT_INDEX 145 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, mmAZALIA_F0_CODEC_ENDPOINT_INDEX 129 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); mmAZALIA_F0_CODEC_ENDPOINT_INDEX 142 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);