mlx5_wqe_eth_seg 410 drivers/infiniband/hw/mlx5/qp.c sizeof(struct mlx5_wqe_eth_seg); mlx5_wqe_eth_seg 4098 drivers/infiniband/hw/mlx5/qp.c struct mlx5_wqe_eth_seg *eseg = *seg; mlx5_wqe_eth_seg 4100 drivers/infiniband/hw/mlx5/qp.c memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); mlx5_wqe_eth_seg 4123 drivers/infiniband/hw/mlx5/qp.c stride = ALIGN(sizeof(struct mlx5_wqe_eth_seg) - mlx5_wqe_eth_seg 4139 drivers/infiniband/hw/mlx5/qp.c *seg += sizeof(struct mlx5_wqe_eth_seg); mlx5_wqe_eth_seg 4140 drivers/infiniband/hw/mlx5/qp.c *size += sizeof(struct mlx5_wqe_eth_seg) / 16; mlx5_wqe_eth_seg 198 drivers/net/ethernet/mellanox/mlx5/core/en.h struct mlx5_wqe_eth_seg eth; mlx5_wqe_eth_seg 28 drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h #define INL_HDR_START_SZ (sizeof(((struct mlx5_wqe_eth_seg *)NULL)->inline_hdr.start)) mlx5_wqe_eth_seg 203 drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h mlx5e_set_eseg_swp(struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg, mlx5_wqe_eth_seg 309 drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c struct mlx5_wqe_eth_seg *eseg = &wqe->eth; mlx5_wqe_eth_seg 51 drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h mlx5e_tx_tunnel_accel(struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg) mlx5_wqe_eth_seg 136 drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.c struct mlx5_wqe_eth_seg *eseg, u8 mode, mlx5_wqe_eth_seg 1498 drivers/net/ethernet/mellanox/mlx5/core/en_main.c struct mlx5_wqe_eth_seg *eseg = &wqe->eth; mlx5_wqe_eth_seg 150 drivers/net/ethernet/mellanox/mlx5/core/en_tx.c mlx5e_txwqe_build_eseg_csum(struct mlx5e_txqsq *sq, struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg) mlx5_wqe_eth_seg 274 drivers/net/ethernet/mellanox/mlx5/core/en_tx.c struct mlx5_wqe_eth_seg *eseg; mlx5_wqe_eth_seg 322 drivers/net/ethernet/mellanox/mlx5/core/en_tx.c struct mlx5_wqe_eth_seg cur_eth = wqe->eth; mlx5_wqe_eth_seg 597 drivers/net/ethernet/mellanox/mlx5/core/en_tx.c struct mlx5_wqe_eth_seg *eseg; mlx5_wqe_eth_seg 109 drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.h struct mlx5_wqe_eth_seg eth;