mixercfg          295 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 	u32 mixercfg = 0, mixercfg_ext = 0, mix, ext;
mixercfg          311 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 	mixercfg = CTL_MIXER_BORDER_OUT; /* always set BORDER_OUT */
mixercfg          330 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 					mixercfg |= mix << 0;
mixercfg          338 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 					mixercfg |= mix << 3;
mixercfg          346 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 					mixercfg |= mix << 6;
mixercfg          354 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 					mixercfg |= mix << 26;
mixercfg          359 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 				mixercfg |= mix << 9;
mixercfg          363 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 				mixercfg |= mix << 12;
mixercfg          367 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 				mixercfg |= mix << 15;
mixercfg          371 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 				mixercfg |= mix << 29;
mixercfg          378 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 					mixercfg |= mix << 18;
mixercfg          386 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 					mixercfg |= mix << 21;
mixercfg          419 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 	DPU_REG_WRITE(c, CTL_LAYER(lm), mixercfg);
mixercfg          168 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 			mixer_cfg = mixercfg(mixer_cfg, mdp4_crtc->mixer,