mic_dma_read_reg  428 drivers/dma/mic_x100_dma.c 	if (mic_dma_read_reg(ch, MIC_DMA_REG_DCHERR) ||
mic_dma_read_reg  429 drivers/dma/mic_x100_dma.c 	    mic_dma_read_reg(ch, MIC_DMA_REG_DSTAT) & MIC_DMA_CHAN_QUIESCE) {
mic_dma_read_reg  448 drivers/dma/mic_x100_dma.c 	ch->last_tail = mic_dma_read_reg(ch, MIC_DMA_REG_DTPR);
mic_dma_read_reg  686 drivers/dma/mic_x100_dma.c 			   mic_dma_read_reg(ch, MIC_DMA_REG_DCAR),
mic_dma_read_reg  687 drivers/dma/mic_x100_dma.c 			   mic_dma_read_reg(ch, MIC_DMA_REG_DTPR),
mic_dma_read_reg  688 drivers/dma/mic_x100_dma.c 			   mic_dma_read_reg(ch, MIC_DMA_REG_DHPR),
mic_dma_read_reg  689 drivers/dma/mic_x100_dma.c 			   mic_dma_read_reg(ch, MIC_DMA_REG_DRAR_HI));
mic_dma_read_reg  691 drivers/dma/mic_x100_dma.c 			   mic_dma_read_reg(ch, MIC_DMA_REG_DRAR_LO),
mic_dma_read_reg  692 drivers/dma/mic_x100_dma.c 			   mic_dma_read_reg(ch, MIC_DMA_REG_DCHERR),
mic_dma_read_reg  693 drivers/dma/mic_x100_dma.c 			   mic_dma_read_reg(ch, MIC_DMA_REG_DCHERRMSK),
mic_dma_read_reg  694 drivers/dma/mic_x100_dma.c 			   mic_dma_read_reg(ch, MIC_DMA_REG_DSTAT));
mic_dma_read_reg  197 drivers/dma/mic_x100_dma.h 	return mic_dma_read_reg(ch, MIC_DMA_REG_DSTAT) &
mic_dma_read_reg  246 drivers/dma/mic_x100_dma.h 	u32 dcar = mic_dma_read_reg(ch, MIC_DMA_REG_DCAR);
mic_dma_read_reg  257 drivers/dma/mic_x100_dma.h 	u32 dcar = mic_dma_read_reg(ch, MIC_DMA_REG_DCAR);