mfdcr 106 arch/powerpc/boot/4xx.c banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B0BAS)); mfdcr 109 arch/powerpc/boot/4xx.c banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B1BAS)); mfdcr 112 arch/powerpc/boot/4xx.c banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B2BAS)); mfdcr 115 arch/powerpc/boot/4xx.c banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B3BAS)); mfdcr 297 arch/powerpc/boot/4xx.c while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET) mfdcr 313 arch/powerpc/boot/4xx.c bxcr = mfdcr(DCRN_EBC0_CFGDATA); mfdcr 333 arch/powerpc/boot/4xx.c u32 sys0 = mfdcr(DCRN_CPC0_SYS0); mfdcr 334 arch/powerpc/boot/4xx.c u32 cr0 = mfdcr(DCRN_CPC0_CR0); mfdcr 550 arch/powerpc/boot/4xx.c u32 pllmr = mfdcr(DCRN_CPC0_PLLMR); mfdcr 551 arch/powerpc/boot/4xx.c u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0); mfdcr 552 arch/powerpc/boot/4xx.c u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1); mfdcr 553 arch/powerpc/boot/4xx.c u32 psr = mfdcr(DCRN_405_CPC0_PSR); mfdcr 623 arch/powerpc/boot/4xx.c u32 pllmr0 = mfdcr(DCRN_CPC0_PLLMR0); mfdcr 624 arch/powerpc/boot/4xx.c u32 pllmr1 = mfdcr(DCRN_CPC0_PLLMR1); mfdcr 625 arch/powerpc/boot/4xx.c u32 cpc0_ucr = mfdcr(DCRN_CPC0_UCR); mfdcr 26 arch/powerpc/boot/cuboot-hotfoot.c u32 uart = mfdcr(DCRN_CPC0_UCR) & 0x7f; mfdcr 30 arch/powerpc/boot/dcr.h mfdcr(DCRN_SDRAM0_CFGDATA); }) mfdcr 183 arch/powerpc/boot/dcr.h mfdcr(DCRN_SDR0_CONFIG_DATA); }) mfdcr 201 arch/powerpc/boot/dcr.h mfdcr(DCRN_CPR0_CFGDATA); }) mfdcr 29 arch/powerpc/include/asm/dcr-native.h #define dcr_read_native(host, dcr_n) mfdcr(dcr_n + host.base) mfdcr 72 arch/powerpc/platforms/44x/fsp2.c pr_err("GESR0: 0x%08x\n", mfdcr(base + PLB4OPB_GESR0)); mfdcr 73 arch/powerpc/platforms/44x/fsp2.c pr_err("GESR1: 0x%08x\n", mfdcr(base + PLB4OPB_GESR1)); mfdcr 74 arch/powerpc/platforms/44x/fsp2.c pr_err("GESR2: 0x%08x\n", mfdcr(base + PLB4OPB_GESR2)); mfdcr 75 arch/powerpc/platforms/44x/fsp2.c pr_err("GEARU: 0x%08x\n", mfdcr(base + PLB4OPB_GEARU)); mfdcr 76 arch/powerpc/platforms/44x/fsp2.c pr_err("GEAR: 0x%08x\n", mfdcr(base + PLB4OPB_GEAR)); mfdcr 86 arch/powerpc/platforms/44x/fsp2.c pr_err("BC_SHD: 0x%08x\n", mfdcr(DCRN_PLB6_SHD)); mfdcr 87 arch/powerpc/platforms/44x/fsp2.c pr_err("BC_ERR: 0x%08x\n", mfdcr(DCRN_PLB6_ERR)); mfdcr 90 arch/powerpc/platforms/44x/fsp2.c pr_err("ESR: 0x%08x\n", mfdcr(DCRN_PLB6PLB4_ESR)); mfdcr 91 arch/powerpc/platforms/44x/fsp2.c pr_err("EARH: 0x%08x\n", mfdcr(DCRN_PLB6PLB4_EARH)); mfdcr 92 arch/powerpc/platforms/44x/fsp2.c pr_err("EARL: 0x%08x\n", mfdcr(DCRN_PLB6PLB4_EARL)); mfdcr 95 arch/powerpc/platforms/44x/fsp2.c pr_err("ESR: 0x%08x\n", mfdcr(DCRN_PLB4PLB6_ESR)); mfdcr 96 arch/powerpc/platforms/44x/fsp2.c pr_err("EARH: 0x%08x\n", mfdcr(DCRN_PLB4PLB6_EARH)); mfdcr 97 arch/powerpc/platforms/44x/fsp2.c pr_err("EARL: 0x%08x\n", mfdcr(DCRN_PLB4PLB6_EARL)); mfdcr 100 arch/powerpc/platforms/44x/fsp2.c pr_err("BESR0: 0x%08x\n", mfdcr(DCRN_PLB6MCIF_BESR0)); mfdcr 101 arch/powerpc/platforms/44x/fsp2.c pr_err("BESR1: 0x%08x\n", mfdcr(DCRN_PLB6MCIF_BESR1)); mfdcr 102 arch/powerpc/platforms/44x/fsp2.c pr_err("BEARH: 0x%08x\n", mfdcr(DCRN_PLB6MCIF_BEARH)); mfdcr 103 arch/powerpc/platforms/44x/fsp2.c pr_err("BEARL: 0x%08x\n", mfdcr(DCRN_PLB6MCIF_BEARL)); mfdcr 106 arch/powerpc/platforms/44x/fsp2.c pr_err("P0ESRH 0x%08x\n", mfdcr(DCRN_PLB4_P0ESRH)); mfdcr 107 arch/powerpc/platforms/44x/fsp2.c pr_err("P0ESRL 0x%08x\n", mfdcr(DCRN_PLB4_P0ESRL)); mfdcr 108 arch/powerpc/platforms/44x/fsp2.c pr_err("P0EARH 0x%08x\n", mfdcr(DCRN_PLB4_P0EARH)); mfdcr 109 arch/powerpc/platforms/44x/fsp2.c pr_err("P0EARH 0x%08x\n", mfdcr(DCRN_PLB4_P0EARH)); mfdcr 110 arch/powerpc/platforms/44x/fsp2.c pr_err("P1ESRH 0x%08x\n", mfdcr(DCRN_PLB4_P1ESRH)); mfdcr 111 arch/powerpc/platforms/44x/fsp2.c pr_err("P1ESRL 0x%08x\n", mfdcr(DCRN_PLB4_P1ESRL)); mfdcr 112 arch/powerpc/platforms/44x/fsp2.c pr_err("P1EARH 0x%08x\n", mfdcr(DCRN_PLB4_P1EARH)); mfdcr 113 arch/powerpc/platforms/44x/fsp2.c pr_err("P1EARH 0x%08x\n", mfdcr(DCRN_PLB4_P1EARH)); mfdcr 121 arch/powerpc/platforms/44x/fsp2.c pr_err("ESR: 0x%08x\n", mfdcr(DCRN_PLB4AHB_ESR)); mfdcr 122 arch/powerpc/platforms/44x/fsp2.c pr_err("SEUAR: 0x%08x\n", mfdcr(DCRN_PLB4AHB_SEUAR)); mfdcr 123 arch/powerpc/platforms/44x/fsp2.c pr_err("SELAR: 0x%08x\n", mfdcr(DCRN_PLB4AHB_SELAR)); mfdcr 126 arch/powerpc/platforms/44x/fsp2.c pr_err("\nESR: 0x%08x\n", mfdcr(DCRN_AHBPLB4_ESR)); mfdcr 127 arch/powerpc/platforms/44x/fsp2.c pr_err("\nEAR: 0x%08x\n", mfdcr(DCRN_AHBPLB4_EAR)); mfdcr 139 arch/powerpc/platforms/44x/fsp2.c pr_err("CONF_FIR: 0x%08x\n", mfdcr(DCRN_CONF_FIR_RWC)); mfdcr 140 arch/powerpc/platforms/44x/fsp2.c pr_err("RPERR0: 0x%08x\n", mfdcr(DCRN_CONF_RPERR0)); mfdcr 141 arch/powerpc/platforms/44x/fsp2.c pr_err("RPERR1: 0x%08x\n", mfdcr(DCRN_CONF_RPERR1)); mfdcr 152 arch/powerpc/platforms/44x/fsp2.c mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_MCSTAT)); mfdcr 154 arch/powerpc/platforms/44x/fsp2.c mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_MCOPT1)); mfdcr 156 arch/powerpc/platforms/44x/fsp2.c mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_MCOPT2)); mfdcr 158 arch/powerpc/platforms/44x/fsp2.c mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_PHYSTAT)); mfdcr 160 arch/powerpc/platforms/44x/fsp2.c mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR0)); mfdcr 162 arch/powerpc/platforms/44x/fsp2.c mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR1)); mfdcr 164 arch/powerpc/platforms/44x/fsp2.c mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR2)); mfdcr 166 arch/powerpc/platforms/44x/fsp2.c mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR3)); mfdcr 168 arch/powerpc/platforms/44x/fsp2.c mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_SCRUB_CNTL)); mfdcr 170 arch/powerpc/platforms/44x/fsp2.c mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_ECCERR_PORT0)); mfdcr 172 arch/powerpc/platforms/44x/fsp2.c mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_ECCERR_ADDR_PORT0)); mfdcr 174 arch/powerpc/platforms/44x/fsp2.c mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_ECCERR_COUNT_PORT0)); mfdcr 176 arch/powerpc/platforms/44x/fsp2.c mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_ECC_CHECK_PORT0)); mfdcr 178 arch/powerpc/platforms/44x/fsp2.c mfdcr(DCRN_CW_BASE + DCRN_CW_MCER0)); mfdcr 180 arch/powerpc/platforms/44x/fsp2.c mfdcr(DCRN_CW_BASE + DCRN_CW_MCER1)); mfdcr 182 arch/powerpc/platforms/44x/fsp2.c mfdcr(DCRN_PLB6MCIF_BESR0)); mfdcr 184 arch/powerpc/platforms/44x/fsp2.c mfdcr(DCRN_PLB6MCIF_BEARL)); mfdcr 186 arch/powerpc/platforms/44x/fsp2.c mfdcr(DCRN_PLB6MCIF_BEARH)); mfdcr 249 arch/powerpc/platforms/44x/fsp2.c val = mfdcr(DCRN_PLB6_CR0); mfdcr 256 arch/powerpc/platforms/44x/fsp2.h data = mfdcr(DCRN_CMU_DATA); \ mfdcr 268 arch/powerpc/platforms/44x/fsp2.h data = mfdcr(DCRN_L2CDCRDI); \ mfdcr 36 arch/powerpc/platforms/4xx/soc.c while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC)) mfdcr 39 arch/powerpc/platforms/4xx/soc.c return mfdcr(dcrbase_l2c + DCRN_L2C0_DATA); mfdcr 44 arch/powerpc/platforms/4xx/soc.c u32 sr = mfdcr(dcrbase_l2c + DCRN_L2C0_SR); mfdcr 126 arch/powerpc/platforms/4xx/soc.c mfdcr(dcrbase_isram + DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE); mfdcr 128 arch/powerpc/platforms/4xx/soc.c mfdcr(dcrbase_isram + DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK); mfdcr 130 arch/powerpc/platforms/4xx/soc.c mfdcr(dcrbase_isram + DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK); mfdcr 132 arch/powerpc/platforms/4xx/soc.c mfdcr(dcrbase_isram + DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK); mfdcr 134 arch/powerpc/platforms/4xx/soc.c mfdcr(dcrbase_isram + DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK); mfdcr 137 arch/powerpc/platforms/4xx/soc.c r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG) & mfdcr 146 arch/powerpc/platforms/4xx/soc.c while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC)) mfdcr 153 arch/powerpc/platforms/4xx/soc.c r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP0) & mfdcr 158 arch/powerpc/platforms/4xx/soc.c r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP1) & mfdcr 166 arch/powerpc/platforms/4xx/soc.c r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG); mfdcr 62 arch/powerpc/platforms/4xx/uic.c er = mfdcr(uic->dcrbase + UIC_ER); mfdcr 76 arch/powerpc/platforms/4xx/uic.c er = mfdcr(uic->dcrbase + UIC_ER); mfdcr 102 arch/powerpc/platforms/4xx/uic.c er = mfdcr(uic->dcrbase + UIC_ER); mfdcr 150 arch/powerpc/platforms/4xx/uic.c tr = mfdcr(uic->dcrbase + UIC_TR); mfdcr 151 arch/powerpc/platforms/4xx/uic.c pr = mfdcr(uic->dcrbase + UIC_PR); mfdcr 210 arch/powerpc/platforms/4xx/uic.c msr = mfdcr(uic->dcrbase + UIC_MSR); mfdcr 327 arch/powerpc/platforms/4xx/uic.c msr = mfdcr(primary_uic->dcrbase + UIC_MSR);