mem_reg          1196 arch/mips/include/asm/octeon/cvmx-pow.h 		uint64_t mem_reg:2;
mem_reg          1210 arch/mips/include/asm/octeon/cvmx-pow.h 	        uint64_t mem_reg:2;
mem_reg           195 arch/powerpc/kvm/mpic.c 	const struct mem_reg *mmio_regions[MAX_MMIO_REGIONS];
mem_reg          1247 arch/powerpc/kvm/mpic.c static const struct mem_reg openpic_gbl_mmio = {
mem_reg          1254 arch/powerpc/kvm/mpic.c static const struct mem_reg openpic_tmr_mmio = {
mem_reg          1261 arch/powerpc/kvm/mpic.c static const struct mem_reg openpic_cpu_mmio = {
mem_reg          1268 arch/powerpc/kvm/mpic.c static const struct mem_reg openpic_src_mmio = {
mem_reg          1275 arch/powerpc/kvm/mpic.c static const struct mem_reg openpic_msi_mmio = {
mem_reg          1282 arch/powerpc/kvm/mpic.c static const struct mem_reg openpic_summary_mmio = {
mem_reg          1289 arch/powerpc/kvm/mpic.c static void add_mmio_region(struct openpic *opp, const struct mem_reg *mr)
mem_reg          1345 arch/powerpc/kvm/mpic.c 		const struct mem_reg *mr = opp->mmio_regions[i];
mem_reg          1361 arch/powerpc/kvm/mpic.c 		const struct mem_reg *mr = opp->mmio_regions[i];
mem_reg            52 drivers/infiniband/ulp/iser/iser_initiator.c 	struct iser_mem_reg *mem_reg;
mem_reg            80 drivers/infiniband/ulp/iser/iser_initiator.c 	mem_reg = &iser_task->rdma_reg[ISER_DIR_IN];
mem_reg            83 drivers/infiniband/ulp/iser/iser_initiator.c 	hdr->read_stag = cpu_to_be32(mem_reg->rkey);
mem_reg            84 drivers/infiniband/ulp/iser/iser_initiator.c 	hdr->read_va   = cpu_to_be64(mem_reg->sge.addr);
mem_reg            87 drivers/infiniband/ulp/iser/iser_initiator.c 		 task->itt, mem_reg->rkey,
mem_reg            88 drivers/infiniband/ulp/iser/iser_initiator.c 		 (unsigned long long)mem_reg->sge.addr);
mem_reg           105 drivers/infiniband/ulp/iser/iser_initiator.c 	struct iser_mem_reg *mem_reg;
mem_reg           136 drivers/infiniband/ulp/iser/iser_initiator.c 	mem_reg = &iser_task->rdma_reg[ISER_DIR_OUT];
mem_reg           141 drivers/infiniband/ulp/iser/iser_initiator.c 			hdr->write_stag = cpu_to_be32(mem_reg->rkey);
mem_reg           142 drivers/infiniband/ulp/iser/iser_initiator.c 			hdr->write_va = cpu_to_be64(mem_reg->sge.addr + unsol_sz);
mem_reg           146 drivers/infiniband/ulp/iser/iser_initiator.c 			 task->itt, mem_reg->rkey,
mem_reg           147 drivers/infiniband/ulp/iser/iser_initiator.c 			 (unsigned long long)mem_reg->sge.addr, unsol_sz);
mem_reg           153 drivers/infiniband/ulp/iser/iser_initiator.c 		tx_dsg->addr = mem_reg->sge.addr;
mem_reg           155 drivers/infiniband/ulp/iser/iser_initiator.c 		tx_dsg->lkey = mem_reg->sge.lkey;
mem_reg           440 drivers/infiniband/ulp/iser/iser_initiator.c 	struct iser_mem_reg *mem_reg;
mem_reg           468 drivers/infiniband/ulp/iser/iser_initiator.c 	mem_reg = &iser_task->rdma_reg[ISER_DIR_OUT];
mem_reg           470 drivers/infiniband/ulp/iser/iser_initiator.c 	tx_dsg->addr = mem_reg->sge.addr + buf_offset;
mem_reg           472 drivers/infiniband/ulp/iser/iser_initiator.c 	tx_dsg->lkey = mem_reg->sge.lkey;
mem_reg            45 drivers/infiniband/ulp/iser/iser_memory.c 		      struct iser_mem_reg *mem_reg);
mem_reg            50 drivers/infiniband/ulp/iser/iser_memory.c 		     struct iser_mem_reg *mem_reg);
mem_reg           500 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c 	u32 edc_size, mc_size, mem_reg;
mem_reg           528 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c 	mem_reg = t4_read_reg(adap,
mem_reg           532 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c 	if (mem_reg == 0xffffffff)
mem_reg           535 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c 	*mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
mem_reg           536 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c 	*mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
mem_reg           259 drivers/scsi/csiostor/csio_hw_t5.c 	u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
mem_reg           295 drivers/scsi/csiostor/csio_hw_t5.c 	mem_reg = csio_rd_reg32(hw,
mem_reg           297 drivers/scsi/csiostor/csio_hw_t5.c 	mem_aperture = 1 << (WINDOW_V(mem_reg) + 10);
mem_reg           298 drivers/scsi/csiostor/csio_hw_t5.c 	mem_base = PCIEOFST_G(mem_reg) << 10;
mem_reg           305 drivers/scsi/csiostor/csio_hw_t5.c 		 mem_reg, mem_aperture);