mdp_kms 13 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask, mdp_kms 16 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c mdp4_write(to_mdp4_kms(mdp_kms), REG_MDP4_INTR_CLEAR, mdp_kms 18 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c mdp4_write(to_mdp4_kms(mdp_kms), REG_MDP4_INTR_ENABLE, irqmask); mdp_kms 46 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c struct mdp_kms *mdp_kms = to_mdp_kms(kms); mdp_kms 47 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c struct mdp4_kms *mdp4_kms = to_mdp4_kms(mdp_kms); mdp_kms 54 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c mdp_irq_register(mdp_kms, error_handler); mdp_kms 69 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c struct mdp_kms *mdp_kms = to_mdp_kms(kms); mdp_kms 70 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c struct mdp4_kms *mdp4_kms = to_mdp4_kms(mdp_kms); mdp_kms 82 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c mdp_dispatch_irqs(mdp_kms, status); mdp_kms 20 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h struct mdp_kms base; mdp_kms 158 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask, mdp_kms 15 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask, mdp_kms 18 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_CLEAR, mdp_kms 20 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_EN, irqmask); mdp_kms 52 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c struct mdp_kms *mdp_kms = to_mdp_kms(kms); mdp_kms 53 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms); mdp_kms 64 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c mdp_irq_register(mdp_kms, error_handler); mdp_kms 82 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c struct mdp_kms *mdp_kms = to_mdp_kms(kms); mdp_kms 83 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms); mdp_kms 95 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c mdp_dispatch_irqs(mdp_kms, status); mdp_kms 21 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h struct mdp_kms base; mdp_kms 262 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask, mdp_kms 21 drivers/gpu/drm/msm/disp/mdp_kms.c static void update_irq(struct mdp_kms *mdp_kms) mdp_kms 24 drivers/gpu/drm/msm/disp/mdp_kms.c uint32_t irqmask = mdp_kms->vblank_mask; mdp_kms 28 drivers/gpu/drm/msm/disp/mdp_kms.c list_for_each_entry(irq, &mdp_kms->irq_list, node) mdp_kms 31 drivers/gpu/drm/msm/disp/mdp_kms.c mdp_kms->funcs->set_irqmask(mdp_kms, irqmask, mdp_kms->cur_irq_mask); mdp_kms 32 drivers/gpu/drm/msm/disp/mdp_kms.c mdp_kms->cur_irq_mask = irqmask; mdp_kms 38 drivers/gpu/drm/msm/disp/mdp_kms.c void mdp_irq_update(struct mdp_kms *mdp_kms) mdp_kms 42 drivers/gpu/drm/msm/disp/mdp_kms.c update_irq(mdp_kms); mdp_kms 46 drivers/gpu/drm/msm/disp/mdp_kms.c void mdp_dispatch_irqs(struct mdp_kms *mdp_kms, uint32_t status) mdp_kms 52 drivers/gpu/drm/msm/disp/mdp_kms.c mdp_kms->in_irq = true; mdp_kms 53 drivers/gpu/drm/msm/disp/mdp_kms.c list_for_each_entry_safe(handler, n, &mdp_kms->irq_list, node) { mdp_kms 60 drivers/gpu/drm/msm/disp/mdp_kms.c mdp_kms->in_irq = false; mdp_kms 61 drivers/gpu/drm/msm/disp/mdp_kms.c update_irq(mdp_kms); mdp_kms 66 drivers/gpu/drm/msm/disp/mdp_kms.c void mdp_update_vblank_mask(struct mdp_kms *mdp_kms, uint32_t mask, bool enable) mdp_kms 72 drivers/gpu/drm/msm/disp/mdp_kms.c mdp_kms->vblank_mask |= mask; mdp_kms 74 drivers/gpu/drm/msm/disp/mdp_kms.c mdp_kms->vblank_mask &= ~mask; mdp_kms 75 drivers/gpu/drm/msm/disp/mdp_kms.c update_irq(mdp_kms); mdp_kms 87 drivers/gpu/drm/msm/disp/mdp_kms.c void mdp_irq_wait(struct mdp_kms *mdp_kms, uint32_t irqmask) mdp_kms 96 drivers/gpu/drm/msm/disp/mdp_kms.c mdp_irq_register(mdp_kms, &wait.irq); mdp_kms 99 drivers/gpu/drm/msm/disp/mdp_kms.c mdp_irq_unregister(mdp_kms, &wait.irq); mdp_kms 102 drivers/gpu/drm/msm/disp/mdp_kms.c void mdp_irq_register(struct mdp_kms *mdp_kms, struct mdp_irq *irq) mdp_kms 111 drivers/gpu/drm/msm/disp/mdp_kms.c list_add(&irq->node, &mdp_kms->irq_list); mdp_kms 112 drivers/gpu/drm/msm/disp/mdp_kms.c needs_update = !mdp_kms->in_irq; mdp_kms 118 drivers/gpu/drm/msm/disp/mdp_kms.c mdp_irq_update(mdp_kms); mdp_kms 121 drivers/gpu/drm/msm/disp/mdp_kms.c void mdp_irq_unregister(struct mdp_kms *mdp_kms, struct mdp_irq *irq) mdp_kms 131 drivers/gpu/drm/msm/disp/mdp_kms.c needs_update = !mdp_kms->in_irq; mdp_kms 137 drivers/gpu/drm/msm/disp/mdp_kms.c mdp_irq_update(mdp_kms); mdp_kms 18 drivers/gpu/drm/msm/disp/mdp_kms.h struct mdp_kms; mdp_kms 22 drivers/gpu/drm/msm/disp/mdp_kms.h void (*set_irqmask)(struct mdp_kms *mdp_kms, uint32_t irqmask, mdp_kms 37 drivers/gpu/drm/msm/disp/mdp_kms.h #define to_mdp_kms(x) container_of(x, struct mdp_kms, base) mdp_kms 39 drivers/gpu/drm/msm/disp/mdp_kms.h static inline void mdp_kms_init(struct mdp_kms *mdp_kms, mdp_kms 42 drivers/gpu/drm/msm/disp/mdp_kms.h mdp_kms->funcs = funcs; mdp_kms 43 drivers/gpu/drm/msm/disp/mdp_kms.h INIT_LIST_HEAD(&mdp_kms->irq_list); mdp_kms 44 drivers/gpu/drm/msm/disp/mdp_kms.h msm_kms_init(&mdp_kms->base, &funcs->base); mdp_kms 64 drivers/gpu/drm/msm/disp/mdp_kms.h void mdp_dispatch_irqs(struct mdp_kms *mdp_kms, uint32_t status); mdp_kms 65 drivers/gpu/drm/msm/disp/mdp_kms.h void mdp_update_vblank_mask(struct mdp_kms *mdp_kms, uint32_t mask, bool enable); mdp_kms 66 drivers/gpu/drm/msm/disp/mdp_kms.h void mdp_irq_wait(struct mdp_kms *mdp_kms, uint32_t irqmask); mdp_kms 67 drivers/gpu/drm/msm/disp/mdp_kms.h void mdp_irq_register(struct mdp_kms *mdp_kms, struct mdp_irq *irq); mdp_kms 68 drivers/gpu/drm/msm/disp/mdp_kms.h void mdp_irq_unregister(struct mdp_kms *mdp_kms, struct mdp_irq *irq); mdp_kms 69 drivers/gpu/drm/msm/disp/mdp_kms.h void mdp_irq_update(struct mdp_kms *mdp_kms);