mdp5_write 73 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_CONFIG_VSYNC(pp_id), cfg); mdp5_write 74 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_write(mdp5_kms, mdp5_write 76 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_write(mdp5_kms, mdp5_write 78 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_write(mdp5_kms, REG_MDP5_PP_RD_PTR_IRQ(pp_id), mode->vdisplay + 1); mdp5_write 79 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_write(mdp5_kms, REG_MDP5_PP_START_POS(pp_id), mode->vdisplay); mdp5_write 80 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_THRESH(pp_id), mdp5_write 108 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_write(mdp5_kms, REG_MDP5_PP_TEAR_CHECK_EN(pp_id), 1); mdp5_write 119 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_write(mdp5_kms, REG_MDP5_PP_TEAR_CHECK_EN(pp_id), 0); mdp5_write 207 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, data); mdp5_write 209 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, mdp5_write 211 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1); mdp5_write 331 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(lm, mdp5_write 333 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm, mdp5_write 335 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm, mdp5_write 338 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(r_lm, mdp5_write 340 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(r_lm, mdp5_write 342 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(r_lm, mdp5_write 348 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), mdp5_write 352 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm), mdp5_write 386 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(lm), mdp5_write 393 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), val); mdp5_write 398 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(r_lm), mdp5_write 405 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm), val); mdp5_write 832 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride); mdp5_write 833 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm), mdp5_write 835 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm), mdp5_write 838 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm), mdp5_write 841 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(lm), mdp5_write 844 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_XY(lm), mdp5_write 847 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm), mdp5_write 852 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg); mdp5_write 88 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c mdp5_write(mdp5_kms, reg, data); mdp5_write 131 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, intf_sel); mdp5_write 596 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c mdp5_write(mdp5_kms, REG_MDP5_SPARE_0, 0); mdp5_write 609 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c mdp5_write(mdp5_kms, REG_MDP5_SPARE_0, mdp5_write 167 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_CTL(intf), mdp5_write 170 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_PERIOD_F0(intf), vsync_period); mdp5_write 171 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_LEN_F0(intf), vsync_len); mdp5_write 172 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_HCTL(intf), mdp5_write 175 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VSTART_F0(intf), display_v_start); mdp5_write 176 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VEND_F0(intf), display_v_end); mdp5_write 177 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_BORDER_COLOR(intf), 0); mdp5_write 178 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_UNDERFLOW_COLOR(intf), 0xff); mdp5_write 179 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_SKEW(intf), dtv_hsync_skew); mdp5_write 180 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_POLARITY_CTL(intf), ctrl_pol); mdp5_write 181 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_HCTL(intf), mdp5_write 184 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_VSTART_F0(intf), 0); mdp5_write 185 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_VEND_F0(intf), 0); mdp5_write 186 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_PANEL_FORMAT(intf), format); mdp5_write 187 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(intf), 0x3); /* frame+line? */ mdp5_write 211 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intfn), 0); mdp5_write 245 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intfn), 1); mdp5_write 374 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, 0); mdp5_write 375 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, data); mdp5_write 376 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1); mdp5_write 18 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_CLEAR, mdp5_write 20 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_EN, irqmask); mdp5_write 45 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0xffffffff); mdp5_write 46 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000); mdp5_write 76 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000); mdp5_write 91 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, status); mdp5_write 59 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0); mdp5_write 720 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0); mdp5_write 722 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3); mdp5_write 540 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe), mdp5_write 544 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe), mdp5_write 548 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe), mdp5_write 550 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe), mdp5_write 552 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe), mdp5_write 554 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe), mdp5_write 564 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value); mdp5_write 582 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode); mdp5_write 585 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe), mdp5_write 588 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe), mdp5_write 591 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe), mdp5_write 594 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe), mdp5_write 597 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe), mdp5_write 604 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i), mdp5_write 608 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i), mdp5_write 612 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i), mdp5_write 615 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i), mdp5_write 784 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr); mdp5_write 785 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb); mdp5_write 786 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req); mdp5_write 834 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe), mdp5_write 838 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe), mdp5_write 842 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe), mdp5_write 846 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe), mdp5_write 850 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe), mdp5_write 854 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe), mdp5_write 866 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe), mdp5_write 872 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe), mdp5_write 879 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0); mdp5_write 887 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe), mdp5_write 889 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe), mdp5_write 891 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe), mdp5_write 893 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe), mdp5_write 895 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe), mdp5_write 898 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe), mdp5_write 265 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_W_REG(i), mdp5_write 267 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_R_REG(i), mdp5_write 281 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(pipe), mdp5_write 283 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(pipe), mdp5_write 285 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(pipe),