mdp5_pipe         535 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t __offset_PIPE(enum mdp5_pipe idx)
mdp5_pipe         554 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
mdp5_pipe         556 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE(i0); }
mdp5_pipe         571 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0); }
mdp5_pipe         573 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0); }
mdp5_pipe         575 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0); }
mdp5_pipe         577 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + __offset_PIPE(i0); }
mdp5_pipe         591 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + __offset_PIPE(i0); }
mdp5_pipe         605 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + __offset_PIPE(i0); }
mdp5_pipe         619 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + __offset_PIPE(i0); }
mdp5_pipe         633 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + __offset_PIPE(i0); }
mdp5_pipe         641 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
mdp5_pipe         643 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
mdp5_pipe         657 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
mdp5_pipe         659 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
mdp5_pipe         673 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
mdp5_pipe         675 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
mdp5_pipe         683 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
mdp5_pipe         685 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
mdp5_pipe         693 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
mdp5_pipe         707 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset_PIPE(i0); }
mdp5_pipe         721 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(i0); }
mdp5_pipe         735 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIPE(i0); }
mdp5_pipe         749 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(i0); }
mdp5_pipe         763 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PIPE(i0); }
mdp5_pipe         765 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PIPE(i0); }
mdp5_pipe         767 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PIPE(i0); }
mdp5_pipe         769 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PIPE(i0); }
mdp5_pipe         771 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset_PIPE(i0); }
mdp5_pipe         785 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset_PIPE(i0); }
mdp5_pipe         799 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __offset_PIPE(i0); }
mdp5_pipe         801 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_PIPE(i0); }
mdp5_pipe         855 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_PIPE(i0); }
mdp5_pipe         881 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_PIPE(i0); }
mdp5_pipe         898 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0); }
mdp5_pipe         900 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset_PIPE(i0); }
mdp5_pipe         902 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PIPE(i0); }
mdp5_pipe         904 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __offset_PIPE(i0); }
mdp5_pipe         906 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __offset_PIPE(i0); }
mdp5_pipe         908 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __offset_PIPE(i0); }
mdp5_pipe         910 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __offset_PIPE(i0); }
mdp5_pipe         912 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __offset_PIPE(i0); }
mdp5_pipe         914 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __offset_PIPE(i0); }
mdp5_pipe         916 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __offset_PIPE(i0); }
mdp5_pipe         918 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __offset_PIPE(i0); }
mdp5_pipe         920 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_PIPE(i0); }
mdp5_pipe         943 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
mdp5_pipe         945 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
mdp5_pipe         971 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000004 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
mdp5_pipe         997 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000008 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
mdp5_pipe        1011 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0); }
mdp5_pipe        1051 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __offset_PIPE(i0); }
mdp5_pipe        1053 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __offset_PIPE(i0); }
mdp5_pipe        1055 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 + __offset_PIPE(i0); }
mdp5_pipe        1057 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c + __offset_PIPE(i0); }
mdp5_pipe        1059 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __offset_PIPE(i0); }
mdp5_pipe        1061 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __offset_PIPE(i0); }
mdp5_pipe         227 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	enum mdp5_pipe stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } };
mdp5_pipe         228 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	enum mdp5_pipe r_stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } };
mdp5_pipe         246 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 		enum mdp5_pipe right_pipe;
mdp5_pipe         286 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c static u32 mdp_ctl_blend_mask(enum mdp5_pipe pipe,
mdp5_pipe         306 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c static u32 mdp_ctl_blend_ext_mask(enum mdp5_pipe pipe,
mdp5_pipe         348 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 		   enum mdp5_pipe stage[][MAX_PIPE_STAGE],
mdp5_pipe         349 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 		   enum mdp5_pipe r_stage[][MAX_PIPE_STAGE],
mdp5_pipe         438 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c u32 mdp_ctl_flush_mask_pipe(enum mdp5_pipe pipe)
mdp5_pipe          56 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h 		   enum mdp5_pipe stage[][MAX_PIPE_STAGE],
mdp5_pipe          57 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h 		   enum mdp5_pipe r_stage[][MAX_PIPE_STAGE],
mdp5_pipe          67 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h u32 mdp_ctl_flush_mask_pipe(enum mdp5_pipe pipe);
mdp5_pipe         802 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 		const enum mdp5_pipe *pipes, const uint32_t *offsets,
mdp5_pipe         827 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	static const enum mdp5_pipe rgb_planes[] = {
mdp5_pipe         830 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	static const enum mdp5_pipe vig_planes[] = {
mdp5_pipe         833 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	static const enum mdp5_pipe dma_planes[] = {
mdp5_pipe         836 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	static const enum mdp5_pipe cursor_planes[] = {
mdp5_pipe         194 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h static inline const char *pipe2name(enum mdp5_pipe pipe)
mdp5_pipe         208 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h static inline int pipe2nclients(enum mdp5_pipe pipe)
mdp5_pipe         274 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane);
mdp5_pipe         275 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane);
mdp5_pipe         151 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c struct mdp5_hw_pipe *mdp5_pipe_init(enum mdp5_pipe pipe,
mdp5_pipe          18 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h 	enum mdp5_pipe pipe;
mdp5_pipe          42 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h struct mdp5_hw_pipe *mdp5_pipe_init(enum mdp5_pipe pipe,
mdp5_pipe         535 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 			       enum mdp5_pipe pipe,
mdp5_pipe         559 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe)
mdp5_pipe         568 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
mdp5_pipe         744 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
mdp5_pipe         829 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	enum mdp5_pipe pipe = hwpipe->pipe;
mdp5_pipe         920 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	enum mdp5_pipe pipe = hwpipe->pipe;
mdp5_pipe        1029 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane)
mdp5_pipe        1039 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane)
mdp5_pipe          39 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c static inline u32 pipe2client(enum mdp5_pipe pipe, int plane)
mdp5_pipe          97 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c 		enum mdp5_pipe pipe, int nblks)
mdp5_pipe         167 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c 		enum mdp5_pipe pipe, uint32_t blkcfg)
mdp5_pipe         198 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c 		enum mdp5_pipe pipe)
mdp5_pipe         279 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c 		enum mdp5_pipe pipe = hwpipe->pipe;
mdp5_pipe         292 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c 	enum mdp5_pipe pipe;
mdp5_pipe         318 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c 	enum mdp5_pipe pipe;
mdp5_pipe         353 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c 		enum mdp5_pipe pipe = hwpipe->pipe;
mdp5_pipe          80 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h 		enum mdp5_pipe pipe, uint32_t blkcfg);
mdp5_pipe          82 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h 		enum mdp5_pipe pipe);